• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.427-427
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• 2012

Ferroelectric-gate field effect transistor based memory using a nanowire as a conducting channel offers exceptional advantages over conventional memory devices, like small cell size, low-voltage operation, low power consumption, fast programming/erase speed and non-volatility. We successfully fabricated ferroelectric nonvolatile memory devices using both n-type and p-type Si nanowires coated with organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] via a low temperature fabrication process. The devices performance was carefully characterized in terms of their electrical transport, retention time and endurance test. Our p-type Si NW ferroelectric memory devices exhibit excellent memory characteristics with a large modulation in channel conductance between ON and OFF states exceeding $10^5$; long retention time of over $5{\times}10^4$ sec and high endurance of over 105 programming cycles while maintaining ON/OFF ratio higher $10^3$. This result offers a viable way to fabricate a high performance high-density nonvolatile memory device using a low temperature fabrication processing technique, which makes it suitable for flexible electronics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2511-2516
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• 2012

This paper have analyzed the change of threshold voltage for conduction path of double gate(DG) MOSFET. The threshold voltage roll-off among the short channel effects of DGMOSFET have become obstacles of precise device operation. The analytical solution of Poisson's equation have been used to analyze the threshold voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The threshold voltages for conduction path have been analyzed for device parameters such as channel length, channel thickness, gate oxide thickness and doping concentration. Since this potential model has been verified in the previous papers, we have used this model to analyze the threshold voltage. Resultly, we know the threshold voltage is greatly influenced on the change of conduction path for device parameters of DGMOSFET.

• Proceedings of the KSR Conference
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• 2009.05a
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• pp.860-865
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• 2009

This thesis deals with application of Windows CE for Embedded System and the development methode of "Speed Gate Controller Tester" taking advantage of development program. We can improve reliability, stability and convenience of maintenance work as use of "Speed Gate Controller Tester" which was developed and applied "Embedded System" We can provide customers with more qualified service naturally because of the higher rate of operation which makes people use more pleasant and comfortable subway facility. And also it is possible to manage processor, time schedule and hardware resource as application of Embedded System and Windows CE. Embedded System applied OS Windows CE makes it possible to develop other various products, another application of equipment and tester. Thus this paper treats problems the moment developed and the present condition, development process, field application results.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.16 no.3
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• pp.15-27
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• 2017

In general, increasing train dwell time leads to increasing train service frequency, and it in turn contributes to increasing the congestion level of train and platform. Therefore, the studies on train dwell time have received growing attention in the perspective of scheduling train operation. This study develops a prediction model of train dwell time to enable train operators to mitigate platform congestion by metering passenger inflow at platform gate with respect to platform congestion levels in real-time. To estimate the prediction model, three types of independent variables were applied: number of passengers to get into train, number of passengers to get out of trains, and train weights, which are collectable in real-time. The explanatory power of the estimated model was 0.809, and all of the dependent variables were statistically significant at the 99%. As a result, this model can be available for the basis of on-time train service through platform gate metering, which is a strategy to manage passenger inflow at the platform.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1196-1202
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• 2013

This paper have analyzed the change of breakdown voltage for channel doping concentration and device parameters of double gate(DG) MOSFET using two dimensional potential model. The low breakdown voltage becomes the obstacle of power device operation, and breakdown voltage decreases seriously by the short channel effects derived from scaled down device in the case of DGMOSFET. The two dimensional analytical potential distribution derived from Poisson's equation have been used to analyze the breakdown voltage for device parameters such as channel length, channel thickness, gate oxide thickness and channel doping concentration. Resultly, we could observe the breakdown voltage has greatly influenced on device dimensional parameters as well as channel doping concentration, especially the shape of Gaussian function used as channel doping concentration.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Korean Journal of Ecology and Environment
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• v.52 no.1
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• pp.65-70
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• 2019

A total of 23 individuals of glass eel (Anguilla japonica) were investigated from two estuarine barrages of the Nakdong River in 2016. It was observed that most individuals migrated through the eastern barrage, compared to the western. Individual numbers differed significantly along the corridor modification of the barrages; for example, the number of individuals was two to three times higher after the modification. These results indicate that modification of fish way and lock gate for has facilitated migration of glass eel, and our study potentially offers the operation strategy of estuarine barrage in order to induce more active migration of glass eel.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.26 no.1B
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• pp.89-98
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• 2006

In this study, a method for flood runoff analysis in main channel connected with interior floodplain, is applied for evaluation of hydraulics of Sapgyo lake for the purpose of flood protection by considering tidal effect of West Sea and runoff from the watershed. Especially, operational condition of sluice gate was explicitly modeled in conjunction with various runoff scenarios from watershed. The change in hydraulics of main channel and interior floodplain was found to be predominantly affected by tidal effect, and explicit modeling of gate operation made possible the evaluation of hydraulic characteristics of different alternatives. Until now, such an analysis was not made due to the lack of models with such capability, however, with the proposed method, it is possible to perform such an analysis and is thought that the proposed method can be a valuable tool for flood protection planning.

• Journal of Korean Society on Water Environment
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• v.22 no.6
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• pp.1094-1100
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• 2006

In this study, the reservoir sediment reduction methods for long-term operation are proposed by the analysis of both sediment deposit characteristics and sediment reduction effect by each method. To that end, a flowchart for sediment analysis in reservoir is established and sediment deposit is simulated by SMS-SED2D model. The sediment reduction methods which are sediment passing (sluicing), flushing, trapping, bypassing and mechanical removal are used. From the simulation results, the effective method for sediment reduction is operation which is coupled by both sediment passing with sand gate and sediment trapping with debris dam. And If sediment flushing will be used once a year after 50 years, conservation storage can be secured until 100 years after dam construction.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.5
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• pp.703-712
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• 2014

To improve the efficiency and safety of railway systems, the train control system has been considerably evolved from the ground-equipment-based control system (e.g. track circuit, interlocking system, etc.) into the on-board-equipment-based control system. In addition, this train control system enables the rolling stock to intelligently control the trackside facilities by introducing the information and communication technologies (ICT). Accordingly, since the ICT-based train control system makes the railway system be simplified (i.e. the heavy ground-equipment can be removed), the efficient and cost-effective railway system can be realized. In this paper, we perform the feasibility test of the ICT-based train control system via a simulation. To this end, we have developed the prototypes of the on-board controller and wayside object control units which control the point and crossing gate and performed the integrated operation simulation in a testbed. In this paper, before the field test of the on-board-controller-based train control system, we perform the Consecutive operation test for prototypes of the on-board controller, wayside object control units and local control computer.