• Journal of the Optical Society of Korea
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• v.18 no.6
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• pp.639-645
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• 2014

In this paper, the scheme of a single module for simultaneous operation of all-optical computing circuits, namely half adder and half subtractor, are realized using semiconductor optical amplifier (SOA) based logic gates. Optical XOR gate by employing a SOA based Mach-Zehnder interferometer (MZI) configuration is used to get the sum and difference outputs. A carry signal is generated using a SOA-four wave mixing (FWM) based AND gate, whereas, the borrow is generated by employing the SOA-cross gain modulation (XGM) effect. The obtained results confirm the feasibility of our configuration by proving the good level of quality factor i.e. ~5.5, 9.95 and 12.51 for sum/difference, carry and borrow, respectively at 0 dBm of input power.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.11
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• pp.1644-1651
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• 1989

In this paper, a two-dimensional numerical analysis of HEMT's with gate length of 0.6um is performed. In this case, Control Volume Formulation method which has been used in the analysis of heat transfer and fluid flow is used as a numerical method. As a mobility model, empirical formula including the velocithy overshoot phenomena is used instead of two-piece mobility model. The results obtained from this numerical analysis(i.e., the region in which cahnnel is formed, the strength of electric field in the channel, the distribution of potential, and the distribution of electron concentration etc.)are in good agreement with the previous analytic results. And our results also show the parasitic MESFET's operation in the range of the high gate voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.630-634
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• 2016

We report the computer aided design results for a GaSb/InAs broken-gap gate all around nanowire tunneling FET (TFET). In designing, the semi-empirical tight-binding (TB) method using $sp3d5s^*$ is used as band structure model to produce the bulk properties. The calculated band structure is cooperated with open boundary conditions (OBCs) and a three-dimensional $Schr{\ddot{o}}dinger$-Poisson solver to execute quantum transport simulators. We find an device configuration for the operation voltage of 0.3 V which exhibit desired low sub-threshold swing (< 60 mV/dec) by adopting receded gate configuration while maintaining the high current characteristic ($I_{ON}$ > $100 {\mu}A/{\mu}m$) that broken-gap TFETs normally have.

• Journal of Information Display
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• v.7 no.1
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• pp.1-6
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• 2006

A 10" carbon nanotube field emission display device was fabricated with a novel structure with a hopping electron spacer (HES) by screen printing technique. HES plays a role of preventing the broadening of electron beams emitted from carbon nanotubes without electrical discharge during operation. The structure of the novel tetrode is composed of carbon nanotube emitters on a cathode electrode, a gate electrode, an extracting electrode coated on the top side of a HES, and an anode. HES contains funnel-shaped holes of which the inner surfaces are coated with MgO. Electrons extracted through the gate are collected inside the funnel-shaped holes. They hop along the hole surface to the top extracting electrode. In this study the effects of the addition of HES on emission characteristics of field emission display were investigated. An active ozone treatment for the complete removal of residues of organic binders in the emitter devices was applied to the field emission display panel as a post-treatment.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1301-1304
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• 2008

In this study, we used a multiple phase scheme for the clock in the dual-pull-down driver for TFT display panels. In this scheme, the turn-on time for the transistors in the dual-pull-down structure was reduced from 1/2 to 1/4 or 1/8 of the period cycle time. While keeping proper operation of the transistor size of circuit was fine tuned to achieve an optimal performance. The relation between the active time and the transistor dimensions was obtained for the optimal design.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.190-193
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• 2006

we implemented pentacene TFTs able to operate at low voltage less than 2V by using ultrathin Al2O3 layer as a gate insulator. The OTFTs exhibited a mobility of $0.27{\pm}0.05\;cm^2/Vs$, an outstanding subthreshold slope of $0.109{\pm}0.027$, and an on/off current ratio of $2.87{\pm}1.07{\times}10^4$. OTFT operated at low voltage, producing 3.5uA at $V_GS$= 2V and $V_DS$= 1.5V.

• Journal of Information Display
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• v.6 no.1
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• pp.12-16
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• 2005

Gate and data drivers are essential for driving active matrix display. In this study, we integrate drivers with a-Si:H to develop a compact, better reliability and cost effective display. We design and fabricate drivers with conventional a-Si:H thin film transistors (TFTs). The output voltages are investigated according to the input voltage, temperature and operation time. Based on these studies, we propose here a new driver to prevent gate line from the floated state. For the external coupled voltage fluctuation, the proposed driver shows better stability.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.148-150
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• 1993

The IGBT(Insulated Gate Bipolar Transistor) is a power semiconductor device that has gained acceptance among power electronic circuit design engineers for motor drive and Power converter applications. The device-circuit interaction of power insulated gate bipolar transistor for a series-inductor load, both with and without a snubber are, simulated. An analytical model for the transient operation of the IGBT is used in conjunction with the load circuit state equations for the simulations.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1034-1037
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• 2002

A switched-capacitor(SC) type DC-DC converter having capability of integrated circuit fabrication have been marked for the application of mobile equipments. Especially, a ring type SC power supply is featured by the flexible and dynamic voltage conversion ratio change. In this paper, an improvement of the gate driving techniques is proposed for high power efficiency and less area occupation on the chip. Furthermore, its power-saving operation in the stand-by state is proposed. The three-capacitors ring type power supply is really designed and discussed. As results, the simulation results shows the high efficiency of 92.1%, and the higher output put voltage of 10.5 V compared with conventional one of 8.6 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.361-366
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• 2013

A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.