• 제목/요약/키워드: Gate Length

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A Study on the Representations of an Bell Chamber in Namhansansung (남한산성 종(鐘)과 종각(鐘閣) 복원을 위한 연구)

  • Lee, Jin-Hyang;Kim, Dae-Ho;Lee, Jae-Keun
    • Journal of the Korean Institute of Traditional Landscape Architecture
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    • v.28 no.4
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    • pp.120-126
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    • 2010
  • As the importance of an historical area is getting increased in these days, the reconstruction of an bell chamber in Namhansansung has significant historial, educational and cultural meaning. The purpose of this study, as a study on an bell chamber in Namhansansung, is to assume an original location of the bell chamber and identify the size and shape of the original bell chamber through literature study, site inspection, and analysis on old maps. In addition, this study could provide useful information when new bell chamber is constructed. According to the literature study, site inspections(5 times) and analysis on old maps, the original bell chamber is assumed to locate near current Oroji tea house at the rotary, where was in the area of Hanggung. With regard to the traffic system, it is assume that there was an old road along with the current local road No.342 connecting the South Gate with North Gate and a Y or T shape intersection connecting the site of old bell chamber with the north. In addition, there was a government office street from the old bell chamber to Hanggung. The shape of old bell chamber is assumed to have Paljak or Woojingak roof. Samo roof was not found in all the five maps. Regarding the direction of bell chamber, three maps indicate that it faces the East and two maps show that it faces the South. Therefore, it is assumed that the length and width of the roof have similar size. However, a new bell chamber should face the East, which is the same direction with Hanggung. As there is a record which states that a bell in the Cheonheoungsa, Seonggeosan, Cheonan was used as a Namhansansung's bell when the Cheonheoungsa was closed, this study suggests that new Namansansung's bell should be built, considering histroical value and artistry of Cheonheoungsa's bell. This study is a basic research for the reconstruction of Namhansansung in 2009. However, as reconstruction of historical assets should be based on thorough historical evidences. Therefore, more detail researches by a indicator analysis are left for the topic of future studies.

Formation and Development of Abscission Layer between Pedicel and Rachilla, and Changes in Grain Shedding during Ripening in African Rice, Oryza glaberrima Steud (아프리카 벼 Oryza glaberrima의 종실 이층조직의 발달과정과 등숙기간 중 탈립성의 변화)

  • Il Doo, Jin;Yeong Hwan, Bae;Jun, Inouye
    • KOREAN JOURNAL OF CROP SCIENCE
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    • v.40 no.1
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    • pp.103-112
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    • 1995
  • Six African rice varieties, two each from three types having the characteristics of partially, irregularly, and completely developed abscission layers, were selected and grown 1) to investi-gate the histological differences during the formation and development of the abscission layers and 2) to evaluate the changes in the breaking tensile strength required to detach a grain from its pedicel dur-ing ripening period in relation with developmental stage of the abscission layers. In African rice, the panicle and spikelet grew rapidly from 15 days before heading and almost completely grown in length at five days before heading. The abscission regions were recognized at 15 days before heading. However, any apparently developed abscission layers were not recognized in the lemma side for partially developed abscission layers. A group of parenchymatous cells could be observed sporadically in the abscission layers of the lemma side for irregularly developed ab-scission layers. At ten days before heading, abscission layers consisting of one or two layers of parenchymatous cells were clearly distinguished from neighboring cells due to thickened and lignified cell walls. There were a number of individual parenchymatous cells scattered sporadically in the lemma side of partially developed abscission layers, and a number of grouped parenchymatous cells scattered randomly in the lemma side of irregularly developed abscission layers. At two weeks after heading, the grains became almost fully filled. The cracking of abscission layers between rachilla and pedicel was observed, and the breaking tensile strength required to detach a grain from its pedicel was as low as that at harvest time.

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Experimental Study on Effect of Slope and Length of Apron on Discharge through Gate Structure (물받이 길이 및 접근경사에 따른 조력발전 배수구조물 통수능 검토 실험 연구)

  • Yoon, Kwang-Seok;Yeo, Kyu-Dong
    • Proceedings of the Korea Water Resources Association Conference
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    • 2005.05b
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    • pp.1026-1030
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    • 2005
  • 조력발전 건설사업에서 우선적으로 고려되어야 할 사항은 조수간만에 의해 외해부와 조지부 사이를 이동하는 해수를 적절히 소통시키는 것이다. 예를 들어, 단조지 단류식 발전으로 창조시에 발전을 행할 경우, 발전을 행하면서 높아진 조지내의 수위를 다음 발전을 위해서 낮아진 외해수위를 이용하여 효과적으로 배수시키지 못하면 그 시설은 발전효율이 낮아지게 된다. 즉, 수문구조물의 목적은 주어진 조건 하에서 계획된 유량을 충분히 그리고 안전하게 배제시키는 것이다. 본 연구에서는 수문구조물에 대한 물받이의 길이와 경사의 변화에 의한 외해 조위와 시화호 수위차 조건에 따른 유량계수를 구해 배수능력을 검토하고자 하였다. 이를 위해 시화호를 실험대상으로 하여 수리모형을 1:25의 축척비로 제작하였다. 시화방조제를 기준으로 외해부의 조위와 조지부의 수위차를 8가지의 실험조건으로 한 연구를 수행하였다. 유량계수를 산정하기 위하여 8개 실험조건을 계획에서 제시된 수위-조위 조건에서 수위차 및 통수유량을 분배하여 결정하였고, 유량계수 산정식에 따라 상류 흐름 안정지점에서 유속-면적법에 의해서 유량을 측정하였다. 유속은 8개 지점에 대해서 측정하였고, 각 측정지점에서의 측선은 $3\~5$개이며, 측점은 $3\~4$점법으로 수행하였다. 시화호와 외해의 수위차가 1.011m일 때의 수문을 통과하는 유량을 비교한 결과 실험 II와 III의 통과유량은 각각 $1,571m^3/s$$1,515m^3/s$ 의서 실험 I 의 $587m^3/s$에 비해 통수능이 많이 개선되었음을 알 수 있다. 그림 1은 수위차별 유량곡선을 나타내는 것으로, 실험 II에서의 수문의 통수능이 실험 I의 통수능보다 크게 나타남을 알 수 있었다.>일 때가 밸브를 $60\%$$80\%$ 개폐시켰을 때보다 $0.3kg/cm^2,\;0.29kg/cm^2$ 낮게 나타나 밸브를 전체 개방 했을 때 관로내의 수압이 상수설계기준에 적합한 수압을 유지함을 알 수 있다. 상수관로 설계 기준에서는 관로내 수압을 $1.5\~4.0kg/cm^2$으로 나타내고 있는데 $6kg/cm^2$보다 과수압을 나타내는 경우가 $100\%$로 밸브를 개방하였을 때보다 $60\%,\;80\%$ 개방하였을 때가 더 빈번히 발생하고 있으므로 대상지역의 밸브 개폐는 $100\%$ 개방하는 것이 선계기준에 적합한 것으로 나타났다. 밸브 개폐에 따른 수압 변화를 모의한 결과 밸브 개폐도를 적절히 유지하여 필요수량의 확보 및 누수방지대책에 활용할 수 있을 것으로 판단된다.8R(mm)(r^2=0.84)$로 지수적으로 증가하는 경향을 나타내었다. 유거수량은 토성별로 양토를 1.0으로 기준할 때 사양토가 0.86으로 가장 작았고, 식양토 1.09, 식토 1.15로 평가되어 침투수에 비해 토성별 차이가 크게 나타났다. 이는 토성이 세립질일 수록 유거수의 저항이 작기 때문으로 생각된다. 경사에 따라서는 경사도가 증가할수록 증가하였으며 $10\% 경사일 때를 기준으로 $Ro(mm)=Ro_{10}{\times}0.797{\times}e^{-0.021s(\%)}$로 나타났다.천성 승모판 폐쇄 부전등을 초래하는 심각한 선천성 심질환이다. 그러나 진단 즉시 직접 좌관상동맥-대동맥 이식술로 수술적 교정을 해줌으로써 좋은 성적을 기대할 수 있음을 보여주었다.특히 교사들이 중요하게 인식하는 해방적

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Three-Dimensional Video Analysis of the Gate Patterns in Normal Children and Hemiplegic Children with Cerebral Palsy (정상아와 편마비 뇌성마비아의 삼차원 보행분석)

  • Lee Jin-Hee;Bae Sung-Soo;Kim Chung-Sun
    • The Journal of Korean Physical Therapy
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    • v.9 no.1
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    • pp.127-145
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    • 1997
  • The purpose of this study wa9 to analyse the gait patterns of two female children with hemiplegic cerebral palsy by using the three-dimensional video motion analysis technique. Case 1 has mild spastic hemiplegia on the right side while Case 3 has moderate spastic hemiplegia on the left side. A group of 10, normal female children of the same age(7-8 years old) were selected as the control group for comparison. Time and distance variables as well as the Center of Mass displacement, and the pelvic and joint motions in three anatomical planes were analysed for this purpose. The following observations were made through the analysis : Case 1 revealed an asymmetrical gait pattern in which the step length of the unaffected side was shorter than that of the affected side, which wan a result of the effort to minimize loading on the affected leg by shortening the swing phase of the unaffected leg. Case 1 scored similar phase ratios, cadence and walking velocity to the normal group. A slight posterior tilt of the pelvis was observed throughout the gait cycle. Less hip and knee flexion than the normal group was observed, and demonstrated hyperextension of the knee in the terminal stance phase. The main problem in case 1 originated from the insufficient dorsiflexion of the affected foot during the swing phase. Therefore, Case 1 has difficulty with foot clearance in the swing phase. Usually, this is compensated for by using exessive hip abduction and medial rotation in conjuction with trunk elevation as well as increased vortical displacement of the center of mass. Case 1 revealed a foot-flat initial contact pattern. Case 2 was characterized by a consistent retraction ef the affected aide of the body througout the gait cycle, As a result, an asymmetrical gait pattern with increased stance phase ratios of the unaffected side was observed. In spite of this the step lengths of both sieds were similar. Case 2 scored lower cadence and walking speed than the normal group with lower gait stability. The main problem in Case 2 originated from an excessive plantaflexion of the affected foot which, in turn, rebutted in high hip and knee flexion. Hyperextension of the knee was observed at mid-stance, and execessive anterior tilt of the pelvis throughout the gait cycle was noticed. A gait pattern with high hip abduction and medial circumduction was maintained for the stability in the stance phase and foot clearance in the swing phase. Case 2 revealed a forefoot-contact initial contact pattern.

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SOI CMOS Miniaturized Tunable Bandpass Filter with Two Transmission zeros for High Power Application (고 출력 응용을 위한 2개의 전송영점을 가지는 최소화된 SOI CMOS 가변 대역 통과 여파기)

  • Im, Dokyung;Im, Donggu
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.1
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    • pp.174-179
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    • 2013
  • This paper presents a capacitor loaded tunable bandpass chip filter using multiple split ring resonators (MSRRs) with two transmission zeros. To obtain high selectivity and minimize the chip size, asymmetric feed lines are adopted to make a pair of transmission zeros located on each side of passband. Compared with conventional filters using cross-coupling or source-load coupling techniques, the proposed filter uses only two resonators to achieve high selectivity through a pair of transmission zeros. In order to optimize selectivity and sensitivity (insertion loss) of the filter, the effect of the position of asymmetric feed line on transmission zeros and insertion loss is analyzed. The SOI-CMOS switched capacitor composed of metal-insulator-metal (MIM) capacitor and stacked-FETs is loaded at outer rings of MSRRs to tune passband frequency and handle high power signal up to +30 dBm. By turning on or off the gate of the transistors, the passband frequency can be shifted from 4GH to 5GHz. The proposed on-chip filter is implemented in 0.18-${\mu}m$ SOI CMOS technology that makes it possible to integrate high-Q passive devices and stacked-FETs. The designed filter shows miniaturized size of only $4mm{\times}2mm$ (i.e., $0.177{\lambda}g{\times}0.088{\lambda}g$), where ${\lambda}g$ denotes the guided wave length of the $50{\Omega}$ microstrip line at center frequency. The measured insertion loss (S21)is about 5.1dB and 6.9dB at 5.4GHz and 4.5GHz, respectively. The designed filter shows out-of-band rejection greater than 20dB at 500MHz offset from center frequency.

Two-Dimensional Numerical Simulation of GaAs MESFET Using Control Volume Formulation Method (Control Volume Formulation Method를 사용한 GaAs MESFET의 2차원 수치해석)

  • Son, Sang-Hee;Park, Kwang-Mean;Park, Hyung-Moo;Kim, Han-Gu;Kim, Hyeong-Rae;Park, Jang-Woo;Kwack, Kae-Dal
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.1
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    • pp.48-61
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    • 1989
  • In this paper, two-dimensional numerical simulation of GaAs MESFFT with 0.7${\mu}m$ gate length is perfomed. Drift-diffusion model which consider that mobility is a function of local electric field, is used. As a discretization method, instead of FDM (finite difference method) and FEM (finite element method), the Control-Volume Formulation (CVF) is used and as a numerical scheme current hybrid scheme or upwind scheme is replaced by power-law scheme which is very approximate to exponential scheme. In the process of numerical analysis, Peclet number which represents the velocity ratio of drift and diffusion, is introduced. And using this concept a current equation which consider numerical scheme at the interface of control volume, is proposed. The I-V characteristics using the model and numerical method has a good agreement with that of previous paper by others. Therefore, it is confined that it may be useful as a simulator for GaAs MESFET. Besides I-V characteristics, the mechanism of both velocity saturation in drift-diffusion model is described from the view of velocity and electric field distribution at the bottom of the channel. In addition, the relationship between the mechanism and position of dipole and drain current, are described.

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Design and fabrication of the MMIC frequency doubler for 29 GHz local oscillator application (29GHz 국부 발진 신호용 MMIC 주파수 체배기의 설계 및 제작)

  • Kim, Jin-Sung;Lee, Seong-Dae;Lee, Bok-Hyoung;Kim, Sung-Chan;Sul, Woo-Suk;Lim, Byeong-Ok;Kim, Sam-Dong;Park, Hyun-Chang;Park, Hyung-Moo;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.11
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    • pp.63-70
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    • 2001
  • We demonstrate the MMIC (monolithic microwave integrated circuit) frequency doublers generating stable and low-cost 29 GHz local oscillator signals from 14.5 GHz input signals. These devices were designed and fabricated by using the M MIC integration process of $0.1\;{\mu}m$ gate-length PHEMTs (pseudomorphic high electron mobility transistors) and passive components. The measurements showed S11 or -9.2 dB at 145 GHz, S22 of -18.6 dG at 29 GHz and a minimum conversion loss of 18.2 dB at 14.5 GHz with an input power or 6 dBm. Fundamental signal of 14.5 GHz were suppressed below 15.2 dBe compared to the second harmonic signal at the output port, and the isolation characteristics of fundamental signal between the input and the output port were maintained above :i0 dB in the frequency range 10.5 GHz to 18.5 GHz. The chip size of the fabricated MMIC frequency doubler is $1.5{\times}2.2\;mm^2$.

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The Optimization of $0.5{\mu}m$ SONOS Flash Memory with Polycrystalline Silicon Thin Film Transistor (다결정 실리콘 박막 트랜지스터를 이용한 $0.5{\mu}m$ 급 SONOS 플래시 메모리 소자의 개발 및 최적화)

  • Kim, Sang Wan;Seo, Chang-Su;Park, Yu-Kyung;Jee, Sang-Yeop;Kim, Yun-Bin;Jung, Suk-Jin;Jeong, Min-Kyu;Lee, Jong-Ho;Shin, Hyungcheol;Park, Byung-Gook;Hwang, Cheol Seong
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.10
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    • pp.111-121
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    • 2012
  • In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

A 30 GHz Band Low Noise for Satellite Communications Payload using MMIC Circuits (MMIC 회로를 이용한 위성중계기용 30GHz대 저잡음증폭기 모듈 개발)

  • 염인복;김정환
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.11 no.5
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    • pp.796-805
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    • 2000
  • A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

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Narrow channel effect on the electrical characteristics of AlGaN/GaN HEMT (AlGaN/GaN HEMT의 채널폭 스케일링에 따른 협폭효과)

  • Lim, Jin Hong;Kim, Jeong Jin;Shim, Kyu Hwan;Yang, Jeon Wook
    • Journal of IKEEE
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    • v.17 no.1
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    • pp.71-76
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    • 2013
  • AlGaN/GaN HEMTs (High electron mobility transistors) with narrow channel were fabricated and the effect of channel scaling on the device were investigated. The devices were fabricated using e-beam lithography to have same channel length of $1{\mu}m$ and various channel width from 0.5 to $9{\mu}m$. The sheet resistance of the channel was increased corresponding to the decrease of channel width and the increase was larger at the width of sub-${\mu}m$. The threshold voltage of the HEMT with $1.6{\mu}m$ and $9{\mu}m$ channel width was -2.85 V. The transistor showed a variation of 50 mV at the width of $0.9{\mu}m$ and the variation 350 mV at $0.5{\mu}m$. The transconductance of 250 mS/mm was decreased to 150 mS/mm corresponding to the decrease of channel width. Also, the gate leakage current of the HEMT decreased with channel width. But the degree of was reduced at the width of sub-${\mu}m$. It was thought that the variation of the electrical characteristics of the HEMT corresponding to the channel width came from the reduced Piezoelectric field of the AlGaN/GaN structure by the strain relief.