• Progress in Medical Physics
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• v.20 no.4
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• pp.216-224
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• 2009

$^{131}I$ is a radiological isotope being used widely for treatment of cancer as emitting gamma-ray and it is also applied to estimate the function of thyroid for its accumulation in thyroid. However, $^{131}I$ is more difficult to quantitate comapred to $^{99m}Tc$, because $^{131}I$ has multiple energy gamma-ray emissions compared to $^{99m}Tc$ which is a mono energetic gamma-ray source. Especially, scattered ray and septal penetration resulted by high energy gamma ray have a bad influence upon nuclear medicine image. The purpose of this study was to estimate scatter components depending on the different source locations within a phantom using Monte Carlo simulation (GATE). The simulation results were validated by comparing with the results of real experiments. Dual-head gamma camera (ECAM, Chicago, Illinois Siemens) with high energy, general-purpose, and parallel hole collimators (hole radius: 0.17 cm, septal thickness: 0.2 cm, length: 5.08 cm) was used in this experiment. The NaI crystal is $44.5{\times}59.1\;cm$ in height and width and 0.95 cm in thickness. The diameter and height of PMMA phantom were 16 cm and 15 cm, respectively. The images were acquired at 5 different locations of $^{131}I$ point source within the phantom and the images of $^{99m}Tc$ were also acquired for comparison purpose with low energy source. The simulation results indicated that the scattering was influenced by the location of source within a phantom. The scattering effects showed the same tendency in both simulation and actual experiment, and the results showed that the simulation was very adequate for further studies. The results supported that the simulation techniques may be used to generalize the scattering effects as a function of a point source location within a phantom.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2899-2904
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• 2015

This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.537-539
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• 2006

We developed an 4.5" $192{\times}64$ active matrix organic light-emitting diode display on a glass using organic thin-film transistor (OTFT) switching-arrays with two transistors and a capacitor in each sub-pixel. The OTFTs has bottom contact structure with a unique gate insulator and pentacene for the active layer. The width and length of the switching OTFT is $800{\mu}m$ and $10{\mu}m$ respectively and the driving OTFT has $1200{\mu}m$ channel width with the same channel length. On/off ratio, mobility, on-current of switching OTFT and on-current of driving OTFT were $10^6,0.3{\sim}0.5\;cm^2/V{\cdot}sec$, order of 10 ${\mu}A$ and over 100 ${\mu}A$, respectively. AMOLEDs composed of the OTFT switching arrays and OLEDs made using vacuum deposition method were fabricated and driven to make moving images, successfully.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.50-57
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• 2009

This paper proposes a VLSI architecture of CAVLC hardware decoder which is a tool eliminating statistical redundancy in H.264/AVC video compression. The previous CAVLC hardware decoder used four stages to decode five code symbols. The previous CAVLC hardware architectures decreased decoding performance because there was an unnecessary idle cycle in between state transitions. Likewise, the computation of valid bit length includes an unnecessary idle cycle. This paper proposes hardware architecture to eliminate the idle cycle efficiently. Two methods are applied to the architecture. One is a method which eliminates an unnecessary things of buffers storing decoded codes and then makes efficient pipeline architecture. The other one is a shifter control to simplify operations and controls in the process of calculating valid bit length. The experimental result shows that the proposed architecture needs only 89 cycle in average for one macroblock decoding. This architecture improves the performance by about 29% than previous designs. The synthesis result shows that the design achieves the maximum operating frequency at 140Mhz and the hardware cost is about 11.5K under a 0.18um CMOS process. Comparing with the previous design, it can achieve low-power operation because this design is implemented with high throughputs and low gate count.

• International Journal of Highway Engineering
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• v.14 no.3
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• pp.173-182
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• 2012

Entry and exits of the rest area are sections where designed speed can be rapidly change and also a weak traffic safety section. In addition, two tasks can be performed simultaneously at entry of the rest area, particularly searching for deceleration and parking spaces/parking sides etc. Thus, design criteria is required in order to procure the stability of accessed vehicle. In case of Korea, geometric structure design criteria of entry facilities, such as toll-gate, interchange, junction etc was established. However there are no presence in a detailed standards for geometric structure of the rest area which affiliated road facilities. In this study, Derive problems in regards to the entry of geometric structure of resting areas by utilizing a sight survey and an investigation research of traffic accidents. The survey was targeting 135 general service areas. After Classifying the design section of resting areas' entry as well as derive design elements on each section, a speed measurement by targeting entry of rest areas and car behavior surveys were performed, then each element's minimum standard was derived through the analyses. According to the speeds at the starting/end point of entrance connector road, the minimum length of the entrance connector road is decided as 40m using Slowing-down length formula and based on the driving pattern, the range of the junction setting angle of the entrance connector road is defined as $12^{\circ}{\sim}17^{\circ}$. Suggest improvement plans for existing rest areas that can be applied realistically. This should be corresponded to the standards of entry and exit of developed rest areas.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.713-716
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• 2013

The device performances of N-channel Tunneling FET have been characterized with different intrinsic length between drain and gate($L_{in}$), drain and source doping, permittivity and oxide thickness when the total effective channel length is constant. N-channel Tunneling FET of SOI structure have been used in characterization. $L_{in}$ was from 30nm to 70nm, dose concentration of drain and source were from $2{\times}10^{12}cm^{-2}$ to $2{\times}10^{15}cm^{-2}$ and from $1{\times}10^{14}cm^{-2}$ to $3{\times}10^{15}cm^{-2}$, permittivity was from 3.9 to 29, and oxide thickness was from 3nm to 9nm. The device performances were characterized by Subthreshold slope(S-slope), On/off ratio, and leakage current. From the simulation results, the leakage current have been reduced for long $L_{in}$ and low drain doping. S-slope have been reduced for high source doping, high permittivity and thin oxide thickness. With considering the leakage current and S-slope, it is desirable that are long $L_{in}$, low drain doping, high source doping, high permittivity and thin oxide thickness to optimize device performance in n-channel Tunneling FET.

• Journal of Radiation Industry
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• v.6 no.1
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• pp.31-40
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• 2012

There are two methods to fabricate the readout electronic to a large-area CMOS image sensor (LACIS). One is to design and manufacture the sensor part and signal processing electronics in a single chip and the other is to integrate both parts with bump bonding or wire bonding after manufacturing both parts separately. The latter method has an advantage of the high yield because the optimized and specialized fabrication process can be chosen in designing and manufacturing each part. In this paper, LACIS chip, that is optimized design for the latter method of fabrication, is presented. The LACIS chip consists of a 3-TR pixel photodiode array, row driver (or called as a gate driver) circuit, and bonding pads to the external readout ICs. Among 4 types of the photodiode structure available in a standard CMOS process, $N_{photo}/P_{epi}$ type photodiode showed the highest quantum efficiency in the simulation study, though it requires one additional mask to control the doping concentration of $N_{photo}$ layer. The optimized channel widths and lengths of 3 pixel transistors are also determined by simulation. The select transistor is not significantly affected by channel length and width. But source follower transistor is strongly influenced by length and width. In row driver, to reduce signal time delay by high capacitance at output node, three stage inverter drivers are used. And channel width of the inverter driver increases gradually in each step. The sensor has very long metal wire that is about 170 mm. The repeater consisted of inverters is applied proper amount of pixel rows. It can help to reduce the long metal-line delay.

• Smart Media Journal
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• v.11 no.10
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• pp.65-75
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• 2022

Deep learning is used as a creative tool that could overcome the limitations of existing analysis models and generate various types of results such as text, image, and music. In this paper, we propose a method necessary to preprocess audio data using the Niko's MIDI Pack sound source file as a data set and to generate music using Bi-LSTM. Based on the generated root note, the hidden layers are composed of multi-layers to create a new note suitable for the musical composition, and an attention mechanism is applied to the output gate of the decoder to apply the weight of the factors that affect the data input from the encoder. Setting variables such as loss function and optimization method are applied as parameters for improving the LSTM model. The proposed model is a multi-channel Bi-LSTM with attention that applies notes pitch generated from separating treble clef and bass clef, length of notes, rests, length of rests, and chords to improve the efficiency and prediction of MIDI deep learning process. The results of the learning generate a sound that matches the development of music scale distinct from noise, and we are aiming to contribute to generating a harmonistic stable music.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.41 no.6
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• pp.727-736
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• 2021

Road tunnel lengths are increasing. Some 1,300 tunnels with 1,102 km in length had been increased till 2019 from 2010. There are 64 tunnels over 3,000 m in length, with their total length adding up to 276.7 km. Safety facilities in the event of a tunnel fire are critical so as to prevent large-scale casualties. Standards for installing disaster prevention facilities are being proposed based on the guidelines of the Ministry of Land, Infrastructure and Transport, but they may be limited to deep underground tunnels. This study was undertaken to provide guidelines for the spacing of evacuation connection passages and the widths of evacuation connection doors. Evacuation with various spacing and widths was simulated in regards to evacuation time, which is the measure of safety, using the evacuation analysis simulation software EXODUS Ver.6.3 and the fire/smoke analysis software SMARTFIRE Ver.4.1. Evacuation connection gates with widths of 0.9 m and 1.2 m, and spacings of 150 m to 250 m, were set to every 20 m. In addition, longitudinal slopes of 6 % and 0 % were considered. It was determined to be safe when the evacuation completion time was shorter than the delay diffusion time. According to the simulation results, all occupants could complete evacuation before smoke spread regardless of the width of the evacuation connection door when the longitudinal slope was 6 % and the interval of evacuation connection passage was 150 m. When the evacuation connection passage spacing was 200 m and the evacuation connection gate width was 1.2 m, all occupants could evacuate when the longitudinal slope was 0 %. Due to difference in evacuation speed according to the longitudinal slope, the evacuation time with a 6 % slope was 114 seconds shorter (with the 190 m connection passage) than with a 0 % slope. A shorter spacing of evacuation connection passages may reduce the evacuation time, but this is difficult to implement in practice because of economic and structural limitations. If the width of the evacuation junction is 1.2 m, occupants could evacuate faster than with a 0.9 m width. When the width of a connection door is 1.2 m with appropriate connection passage spacing, it might provide a means to increase economic efficiency and resolve structural limitations while securing evacuation safety.