• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.166-168
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• 2016

이 논문은 포켓 구조 터널링 전계효과 트랜지스터의 구조에 대한 여러 가지 조건을 소개한다. 포켓의 길이는 길어질수록 $I_{on}$이 더 증가하고, 포켓의 두께는 감소할수록 $I_{on}$이 증가하고, 3nm 보다 얇아질 때 SS는 증가한다. 게이트 절연체는 고유전율 물질을 사용하는 것이 적절하다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 춘계학술대회 논문집
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• pp.26-29
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• 1999

The I-V characteristics of the n-channel offset gated poly-Si TETs have been systematically investigated in order to analyse the effects of offset region. The on currents are reduced due to the series resistance by the offset length and there is no kink phenomenon in offset devices. The off currents of the offset gated TFTs are remarkably reduced to 10$^{-12}$ A independent of gate and drain voltage because the electric field is weakened by the increase of the depletion region width near the drain region. It is shown that the offset regions behave as a series resistance and reduce lateral and vertical electric field.

• Journal of the Optical Society of Korea
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• 제18권1호
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• pp.65-70
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• 2014

This paper presents the simulation and design of an all-optical subtractor using a quantum-dot semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA MZI) structure consisting of two cascaded switches, the first of which produces the differential bit. Then the second switch produces the borrow bit by using the output of the first switch and the subtrahend data stream. Simulation results were obtained by solving the rate equations of the QD-SOA. The effects of QD-SOA length, peak power and current density have been investigated. The designed gate can operate at speeds of over 250 Gb/s. The simulation results demonstrate a high extinction ratio and a clear and wide-opening eye diagram.

• ETRI Journal
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• 제33권5호
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• pp.818-821
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• 2011

A D-band subharmonically-pumped resistive mixer has been designed, processed, and experimentally tested. The circuit is based on a $180^{\circ}$ power divider structure consisting of a Lange coupler followed by a ${\lambda}$/4 transmission line (at local oscillator (LO) frequency). This monolithic microwave integrated circuit (MMIC) has been realized in coplanar waveguide technology by using an InAlAs/InGaAs-based metamorphic high electron mobility transistor process with 100-nm gate length. The MMIC achieves a measured conversion loss between 12.5 dB and 16 dB in the radio frequency bandwidth from 120 GHz to 150 GHz with 4-dBm LO drive and an intermediate frequency of 100 MHz. The input 1-dB compression point and IIP3 were simulated to be 2 dBm and 13 dBm, respectively.

• 전기전자학회논문지
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• 제16권2호
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• pp.116-120
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• 2012

본 논문에서는 밀리미터파 응용에 사용 가능한 우수한 성능의 50 nm InGaAs/InAlAs/GaAs metamorphic HEMT를 구현하였다. 게이트 길이가 50 nm이며 단위 게이트 폭이 30 ${\mu}m$인 2개의 게이트를 가지고 있는 MHEMT의 측정결과, 740 mA/mm의 드레인 포화 전류밀도와 1.02 S/mm의 상호전달 전도도를 얻었으며 전류이득차단주파수와 최대공진주파수는 각각 430 GHz와 406 GHz의 특성을 나타내었다.

• 한국통신학회논문지
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• 제21권4호
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• pp.1059-1067
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• 1996

A 128/129 dual-modulus prescalar IC is designed for application to frequency synthesizers in high frequency communication systems. The FET logic used in this design is SCFL(Source Coupled FET Logic), employing depletion-mode 1.mu.m gate length GaAs MESFETs with the threshold voltage of -1.5V. This circuit consists of 8 flip-flops, 3 OR gates, 2 NOR gates, a modulus control buffer and I/O buffers, which are integrated with about 440 GaAs MESFETs on dimensions of 1.8mm. For $V_{DD}$ and $V_{SS}$ power supply voltages 5V and -3.3V Commonly used in TTL and ECL circuits are determined, respectively. The simulation results taking into account the threshold voltage variation of .+-.0.2V and the power supply variation of .+-.1V demonstrate that the designed prescalar can operate up to 2GHz. This prescalar is fabricated using the ETRI MMIC foundary process and the measured maximum operating frquency is 621MHz.

• Transactions on Electrical and Electronic Materials
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• 제12권6호
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• pp.245-248
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• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• Journal of the Optical Society of Korea
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• 제9권3호
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• pp.111-118
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• 2005

In this paper, a new optical parallel binary arithmetic processor (OPBAP) capable of computing arbitrary n-bit look-ahead carry full-addition is proposed and implemented. The conventional Boolean algebra is considered to implement OPBAP by using two schemes of optical logic processor. One is space-variant optical logic gate processor (SVOLGP), the other is shadow-casting optical logic array processor (SCOLAP). SVOLGP can process logical AND and OR operations different in space simultaneously by using free-space interconnection logic filters, while SCOLAP can perform any possible 16 Boolean logic function by using spatial instruction-control filter. A dual-rail encoding method is adopted because the complement of an input is needed in arithmetic process. Experiment on OPBAP for an 8-bit look-ahead carry full addition is performed. The experimental results have shown that the proposed OPBAP has a capability of optical look-ahead carry full-addition with high computing speed regardless of the data length.

• 전기전자학회논문지
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• 제23권3호
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• pp.1015-1019
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• 2019

본 논문에서는 트리거 전압과 감내 특성을 개선시키기 위해 HHVSCR의 구조적 변경을 바탕으로 Stack 기술을 적용한 새로운 ESD 보호 소자를 제안한다. 우선 HHVSCR과 제안된 ESD 보호 소자를 비교하여 트리거 전압과 홀딩 전압, 감내 특성을 확인하였고 게이트 길이에 대한 변수를 추가하였다. 마지막으로, 제안된 ESD 보호 소자와 Stack을 적용한 소자를 비교하여 트리거 전압과 홀딩 전압, 감내 특성을 비교하였다.

• 한국정보통신학회논문지
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• 제24권5호
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.