• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.688-690
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• 2017

항복전압의 감소는 채널길이 감소에 의하여 발생하는 심각한 단채널 효과이다. 트랜지스터 동작 중에 발생하는 단채널 효과는 트랜지스터의 동작범위를 감소시키는 문제를 발생시킨다. 본 논문에서는 10 nm 이하 채널길이를 갖는 이중게이트 MOSFET에서 채널크기의 변화를 파라미터로 하여 채널도핑에 따른 항복전압의 변화를 고찰하였다. 이를 위하여 해석학적 전위분포에 의한 열방사 전류와 터널링 전류를 구하고 두 성분의 합으로 구성된 드레인 전류가 $10{\mu}A$가 될 때, 드레인 전압을 항복전압으로 정의하였다. 결과적으로 채널 도핑농도가 증가할수록 항복전압은 크게 증가하였다. 채널길이가 감소하면서 항복전압이 크게 감소하였으며 이를 해결하기 위하여 실리콘 두께 및 산화막 두께를 매우 작게 유지하여야만 한다는 것을 알 수 있었다. 특히 터널링 전류의 구성비가 증가할수록 항복전압이 증가하는 것을 관찰하였다.

• 한국전기전자재료학회논문지
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• 제37권1호
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• pp.48-55
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• 2024

The changes in threshold voltage and DIBL were investigated for changes in remanent polarization P_r and coercive field E_c, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when P_r decreases and E_c increases, and the threshold voltage is also maintained constant when the P_r/E_c is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to P_r/E_c, so the DIBL greatly changes for P_r/E_c. In other words, when P_r/E_c=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO₂ thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the P_r/E_c is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the P_r and E_c of ferroelectric.

• 대한물리의학회지
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• 제3권4호
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• pp.277-284
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• 2008

Purpose : The purpose of this study was to identify the influence of Bobath and conventional method has an effect on gait of adult hemiplegic patients. Methods : The data were collected by each 15 adult stroke patients. The treatment was based on Bobath and conventional approach. Temporal and spatial parameters of gait were analysed for using the computerized GAITRite system. Results : The gait step (p<.05), gait velocity (p<.05), cadence (p<.05) and step length (p<.05) was significantly different with the Bobath method. The Gait step (p<.05) and gait velocity (p<.05) was significantly different with the conventional method. But the cadence and step length was not significantly increased in the conventional method. Conclusion : The Bobath method is more useful to improve the gait in hemiplegic patients than conventional method.

• 전자공학회논문지A
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• 제33A권11호
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• 대한의용생체공학회:의공학회지
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• 제26권1호
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• pp.17-22
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• 2005

Small animal PET using a dual layer phoswich detector has been developed to obtain high and uniform spatial resolution. In this study, a simple analytic model to optimize the lengths of a dual layer phoswich detector was derived and validated by Monte Carlo simulation. For a small animal PET scanner with a 10㎝ ring diameter, the optimal length of the phoswich detector consisting of various crystal materials, such as LSO and LuYAP, were calculated analytically and validated using GATE. The detector module consisted of 8×8 arrays of crystals, with each phoswich detector element having a 2㎜×2㎜ sensitive area. The total crystal length was fixed to 20㎜. The optimal lengths of the phoswich detector layers, as functions of the crystal materials and order, conveniently derived by the analytic equation, showed good agreement with those estimated by the time consuming simulation. The simple analytical model can be used for the fast and accurate design of an optimal phoswich detector for small animal PET to achieve high spatial resolution and uniformity.

• Current Optics and Photonics
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• 제1권1호
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• pp.65-72
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• 2017

We propose a nearly lossless, compact, electrically modulated vertical directional coupler, which is based on the controllable evanescent coupling in a previously proposed graphene-assisted total internal reflection (GA-FTIR) scheme. In the proposed device, two single-mode waveguides are separate by graphene-$SiO_2$-graphene layers. By changing the chemical potential of the graphene layers with a gate voltage, the coupling strength between the waveguides, and hence the coupling length of the directional coupler, is controlled. Therefore, for a properly chosen, fixed device length, when an input wave is launched into one of the waveguides, the ratio of their output powers can be controlled electrically. The operation of the proposed device is analyzed, with the dispersion relations calculated using a model of a one-dimensional slab waveguide. The supermodes in the coupled waveguide are calculated using the finite-element method to estimate the coupling length, realistic devices are designed, and their performance was confirmed using the finite-difference time-domain method. The designed $3{\mu}m$ by $1{\mu}m$ device achieves an insertion loss of less than 0.11 dB, and a 24-dB extinction ratio between bar and cross states. The proposed low-loss device could enable integrated modulation of a strong optical signal, without thermal buildup.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.169-181
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• 2011

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.12-15
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• 2000

In this paper, we have fabricated the PHEMT's with AlGaAs/InGaAs/GaAs and measured characteristics of DC and frequencies. The PHEMT's has a 0.35$\mu\textrm{m}$ gate length, gate width of 60$\mu\textrm{m}$ and 80$\mu\textrm{m}$, and fingers of 2 and 4. From the measurements results for the 60$\mu\textrm{m}$ ${\times}$ 2 PHEMT's, we obtained 1.2V of Vk, -3.5V of Vp, 46mA of Idss, 221mS/mmof gm, and 3.6dB of S$\sub$21/ gain, 45GHz of f$\sub$T,/ 100GHz of fmax. And, in case of 80$\mu\textrm{m}$ ${\times}$ 4 PHEMT's, we obtained 1.2V of Vk, -4.5V of Vp, 125mA of Idss, 198mS/mm of gm, and 2.0dB of S$\sub$21/ gain. 44GHz of f$\sub$T/, 70GHz of fmax at 35GHz frequency. Also, MAG are decreased as a number of finger are Increased.

• 한국전기전자재료학회논문지
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• 제33권1호
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• pp.78-82
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• 2020

In this study, MOSFETs fabricated on Si-doped, MBE-grown β-Ga₂O₃ are demonstrated. A Si-doped Ga₂O₃ epitaxial layer was grown on a Fe-doped, semi-insulating 1.5 cm × 1 cm Ga₂O₃ substrate using molecular beam epitaxy (MBE). The fabricated devices are circular type MOSFETs with a gate length of 3 ㎛, a source-drain spacing of 20 ㎛, and a gate width of 523 ㎛. The device exhibited a good pinch-off characteristic, a high on-off drain current ratio of approximately 2.7×10⁹, and a high breakdown voltage of 1,080 V, which demonstrates the potential of Ga₂O₃ for power device applications including electric vehicles, railways, and renewable energy.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2000년도 춘계종합학술대회
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• pp.470-473
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• 2000

지난 10여 년 동안 MOSFET는 전력감소, 도핑농도 증가, 캐리어 속도 증가를 위해서 많은 변화를 가져왔다. 이러한 변화를 받아들이기 위해서, 채널의 길이와 공급되어지는 전압이 감소해야만했으며, 그것으로 인해 소자가 더욱 작아지게 되었다. 그러므로 본 논문은 이러한 변화를 위해 채널의 길이와 전압에 의한 MOSFET 구조에서의 변화를 관찰하고, 드레인과 게이트 사이에서의 임팩트 이온화의 변화를 관찰하였다. 본 논문은 세 가지의 모델 즉, conventional MOSFET와 LDD(lightly doped drain) MOSFET, EPI MOSFET을 제시하였다. 게이트 길이는 0.15um, 0.075um을 사용하였고, 스케일링계수는 λ = 2를 사용하였다 스케일링방법은 Constant-Voltage 스케일링으로 하였고, TCAD를 사용하여, 스케일링에 의한 MOSFET의 특성과 임팩트 이온화, 전계를 비교 분석하였으며, 최적의 채널과 도필 농도에 대하여 분석하였다.