• Bulletin of the Korean Chemical Society
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• v.33 no.7
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• pp.2127-2128
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• 2012

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.142.1-142.1
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• 2018

This research presents a new field effect transistor (FET) by using liquid crystal gate dielectric with remote gate. The fabrication of thin-film transistors (TFTs) was used Indium tin oxide (ITO) for the source, drain, and gate electrodes, and indium gallium zinc oxide (IGZO) for the active semiconductor layer. 5CB liquid crystal was used for the gate dielectric material, and the remote gate and active layer were covered with the liquid crystal. The output and transfer characteristics of the LC-gated TFTs were investigated.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.6
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• pp.580-585
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• 2004

Silicon dioxide (SiO$_2$) is widely used as a gate dielectric material for thin film transistors (TFT) and semiconductor devices. In this paper, SiO$_2$ films were grown by APCVD(Atmospheric Pressure chemical vapor deposition) at the high temperature. Experimental investigations were carried out as a function of $O_2$ gas flow ratios from 0 to 200 1pm. This article presents the SiO$_2$ gate dielectric studies in terms of deposition rate, refrative index, FT-IR, C-V for the gate dielectric layer of thin film transistor applications. We also study defect passivation technique for improvement interface or surface properties in thin films. Our passivation technique is Forming Gas Annealing treatment. FGA acts passivation of interface and surface impurity or defects in SiO$_2$ film. We used RTP system for FGA and gained results that reduced surface fixed charge and trap density of midgap value.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.506-508
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• 2005

In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.915-918
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• 2007

We have grown $SiO_2$ film on a polycrystalline Si layer using excited ozone gas, which is produced by ultra-violet light irradiation to ozone gas, without heating substrate. The obtained $SiO_2$ film shows dielectric properties comparable to the device quality films measured at the MIS capacitor configuration.

• Journal of the Korean institute of surface engineering
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• v.41 no.1
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• pp.1-5
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• 2008

In this work, improvement of mechanical and electrical properties of gate dielectric layer for flexible organic thin film transistor (OTFT) devices was investigated. In order to increase the mechanical flexibility of PVP (poly(4-vinyl phenol) organic gate dielectric, a very thin inorganic $HfO_2$ layers with the thickness of $5{\sim}20nm$ was inserted in between the spin-coated PVP layers. Insertion of the inorganic $HfO_2$ in the laminated organic/inorganic structure of PVP/$HfO_2$/PVP layer led to a dramatic reduction in the leakage current compared to the pure PVP layer. Under repetitive cyclic bending, the leakage current density of the laminated PVP/$HfO_2$/PVP layer with the thickness of 20-nm $HfO_2$ layer was not changed, while that of the single PVP layer was increased significantly. Mechanical flexibility tests of the OTFT devices by cyclic bending with 5 mm bending radius indicated that the leakage current of the laminated PVP/$HfO_2$(20 nm)/PVP gate dielectric in the device structure was also much smaller than that of the single PVP layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.9-12
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• 2004

This paper investigated the stability of Ta-Mo alloy on thin gate dielectric. Ta-Mo alloy was deposited by using co-sputtering process after thermal growing of 3.4nm and 4.2nm silicon dioxide. When the sputtering power of Ta and Mo were 100W and 70W, respectively, the suitable work function for NMOS gate electrode, 4.2eV, could obtain. To prove interface thermal stability of thin film gate dielectric and Ta-Mo alloy, rapid thermal annealing was performed at $600^{\circ}C$ and $700^{\circ}C$ for 10sec in Ar ambient. The results of interface reaction were surveyed by change of silicon dioxide thickness and work function after annealing process. Also, the reliability of alloy gate and gate dielectric could be confirmed by quantity of leakage current. Ta-Mo alloy was showed low sheet resistance and thermal stability, namely, little change of gate dielectric and work function, after $700^{\circ}C$ annealing process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.144-147
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• 2003

Cu+ ions drift diffusion in formal oxide film and SiOCH film for interlayer dielectric is evaluated. The diffusion is investigated by measuring shift in the flatband voltage of capacitance/voltage measurements on Cu gate capacitors after bias temperature stressing. At a field of 0.2MV/cm and temperature $200^{\circ}C,\;300^{\circ}C,\;400^{\circ}C,\;500^{\circ}C$ for 10min, 30min, 60min. The Cu+ ions drift rate of $SiOCH(k=2.85{\pm}0.03)$ film is considerable lower than termal oxide. As a result of the experiment, SiOCH film is higher than Thermal oxide film for Cu+ drift diffusion resistance. The important conclusion is that SiOCH film will solve a causing reliability problems aganist Cu+ drift diffuion in dielectric materials.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.158-158
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• 2009

This paper focuses on improving organic thin film transistor (OTFT) characteristics by controlling the self-organization of pentacene molecules with an alignable high-dielectric-constant film. The process, based on the growth of pentacene film through high-vacuum sublimation, is a method of self-organization using ion-beam (IB) bombardment of the $HfO_2/Al_2O_3$ surface used as the gate dielectric layer. X-ray photoelectron spectroscopy indicates that the IB raises the rate of the structural anisotropy of the $HfO_2/Al_2O_3$film, and X-ray diffraction patterns show the possibility of increasing the anisotropy to create the self-organization of pentacene molecules in the first polarized monolayer. An effective mobility of $2.3{\times}10^{-3}cm^2V^{-1}s^{-1}$ was achieved, which is significantly different from that of pentacene films that are not aligned. The proposed OTFT devices with an ultrathin $HfO_2$ structure as the gate dielectric layer were operated at a gate voltage lower than 5 V.

• Current Applied Physics
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• v.18 no.12
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• pp.1546-1552
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• 2018

The polymer nanocomposite as a gate dielectric film was prepared via sol-gel method. The formation of crosslinked structure among nanofillers and polymer matrix was proved by Fourier transform infrared spectroscopy (FT-IR). Differential thermal analysis (DTA) results showed significant increase in the thermal stability of the nanocomposite with respect to that of pure polymer. The nanocomposite films deposited on the p- and n-type Si substrates formed very smooth surface with rms roughness of 0.045 and 0.058 nm respectively. Deconvoluted $Si_{2s}$ spectra revealed the domination of the Si-OH hydrogen bonds and Si-O-Si covalence bonds in the structure of the nanocomposite film deposited on the p- and n-type Si semiconductor layers respectively. The fabricated n-channel field-effect-transistor (FET) showed the low threshold voltage and leakage currents because of the stronger connection between the nanocomposite and n-type Si substrate. Whereas, dominated hydroxyl groups in the nanocomposite dielectric film deposited on the p-type Si substrate increased trap states in the interface, led to the drop of FET operation.