• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.83-87
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• 2002

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride ($SiN_X$) is widely used as a gate dielectric material for the hydrogenated amorphous silicon(a-Si:H) thin film transistors (TFT's). We investigated $SiN_X$ films were deposited PECVD at low temperature ($300^{\circ}C$). The reaction gases were used pure nitrogen and a helium diluted of silane gas(20% $SiH_4$, 80% He). Experimental investigations were carried out with the variation of $N_2/SiH_4$ flow ratios from 3 to 50 and the rf power of 200 W. This article presents the $SiN_X$ gate dielectric studies in terms of deposition rate, hydrogen content, etch rate and C-V, leakage current density characteristics for the gate dielectric layer of thin film transistor applications. Electrical properties were analyzed through high frequency (1MHz) C-V and current-voltage (I-V) measurements. The thickness and the refractive index on the films were measured by ellipsometry and chemical bonds were determined by using an FT-IR equipment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.1
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• pp.12-16
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• 2011

In this study, we fabricated the flexible pentacene TFTs with the polymer gate dielectric and contact printing method by using the silver nano particle ink as a source/drain material on plastic substrate. In this experiment, to lower the cross-linking temperature of the PVP gate dielectric, UV-Ozone treatment has been used and the process temperature is lowered to $90^{\circ}C$ and the surface is optimized by various treatment to improve device characteristics. We tried various surface treatments; $O_2$ Plasma, hexamethyl-disilazane (HMDS) and octadecyltrichlorosilane (OTS) treatment methods of gate dielectric/semiconductor interface, which reduces trap states such as -OH group and grain boundary in order to improve the OTFTs properties. The optimized OTFT shows the device performance with field effect mobility, on/off current ratio, and the sub-threshold slope were extracted as $0.63cm^2 V^{-1}s^{-1}$, $1.7{\times}10^{-6}$, and of 0.75 V/decade, respectively.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.29-32
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• 2000

Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO$_{3}$/AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$.cmcm

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.269-271
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• 2005

Using optimized sputtering condition of a-Si and $SiO_2$ thin film, we can obtained the large grained poly-Si film on PES substrate. The gate dielectric grown by plasma enhanced atomic layer deposition, laser activation and organic interlayer dielectric material make TFTs on PES possible with mobility of $11cm^2/Vs$ (nMOS) and $7cm_2/Vs$ (pMOS).

• Proceedings of the KIEE Conference
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• 2000.11c
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• pp.455-457
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• 2000

In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.03a
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• pp.21-21
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• 2010

(Ba,Sr)$TiO_3$ (BST) thin film with a perovskite structure has potential for the practical application in various functional devices such as nonvolatile-memory components, capacitor, gate insulator of thin-film transistors, and electro-optic devices for display. Normally, the BST thin films derived from sol-gel and sputtering are amorphous or partially crystalline when processed below $600^{\circ}C$. For the purpose of integrating BST thin film directly into a Si-based read-out integrated circuit (ROIC), it is necessary to process the BST film below $400^{\circ}C$. The microstructural and electrical properties of low-temperature crystallized BST film were studied. The BST thin films have been fabricated at $350^{\circ}C$ by UV-assisted rapidly thermal annealing (RTA). The BST films are in a single perovskite phase and have well-defined electrical properties such as high dielectric constant, low dielectric loss, low leakage current density, and high breakdown voltage. Photoexcitation of the organics contained in the sol-gel-derived films by high-intensity UV irradiation facilitates elimination of the organics and formation of the single-crystalline phase films at low temperatures. The amorphous BST thin film was transformed to a highly (h00)-oriented perovskite structure by high oxygen pressure processing (HOPP) at as low as $350^{\circ}C$. The dielectric properties of BST film were comparable to (or even better than) those of the conventionally processed BST films prepared by sputtering or post-annealing at temperature above $600^{\circ}C$. When external pressure was applied to the well-known contractive BST system during annealing, the nucleation energy barrier was reduced; correspondingly, the crystallization temperature decreased. The UV-assisted RTA and HOPP, as compatible with existing MOS technology, let the BST films be integrated into radio-frequency circuit and mixed-signal integrated circuit below the critical temperature of $400^{\circ}C$.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• Proceedings of the Korean Vacuum Society Conference
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• 2008.02a
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• pp.306-306
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• 2008

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• Korean Journal of Materials Research
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• v.15 no.3
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• pp.202-208
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• 2005

The surface states of gate dielectrics affect device performance severely in Pentacene OTFTs. We have fabricated organic thin-film transistors (OTFTs) using pentacene as an active layer with chemically modified $SiO_2$ gate dielectrics. The effects of the surface treatment of $SiO_2$ on the electric characteristics of OTFTS were investigated. The surface of $SiO_2$ gate dielectric was treated by normal wet cleaning process, $O_2-plasma$ treatment, hexamethyldisilazane (HMDS), and octadecyltrichlorosilane (OTS) treatment. After the surface treatments, the contact angles and surface free energies were measured in order to analyze the surface state changes. In the electrical measurements, typical I-V characteristics of TFTs were observed. The field effect mobility, $\mu$, was calculated to be $0.29\;cm^2V^{-1}s^{-1}$ for OTS treated sample while those for the HMDS, $O_2$ plasma treated, and wet-cleaned samples were 0.16, 0.1, and $0.04\;cm^2V^{-1}s^{-1}$, respectively.