• Title/Summary/Keyword: Gate Bias Control

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Active control of field emitter arrays with a-Si:H TFTs (비정질 실리콘 박막 트랜지스터에 의한 전계방출기 어레이의 능동제어)

  • 엄현석;송윤호;강승열;정문연;조영래;황치선;이상균;김도형;이진호
    • Proceedings of the IEEK Conference
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    • 2000.11b
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    • pp.33-36
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    • 2000
  • Active-controlled field emitter arrays (ACFEAs) are developed by monolithically integrating molybdenum field emitter arrays with amorphous silicon thin film transistors (a-Si:H TFTs) on glass substrate. Transfer and output characteristics of the fabricated ACFEAs showed that the emission currents of FEAs can be accurately controlled by the gate bias voltages of TFTs. Also, the emission currents of the ACFEAs kept stable without any fluctuations during the 30 min-operation.

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A Study of D.C. Series Motor Control Circuit by Pulsewidth Modulated Chopper (PWM Chopper에 의한 직류직권전동기의 제어회로에 관한 연구)

  • 임달호;장호성
    • 전기의세계
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    • v.26 no.3
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    • pp.76-83
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    • 1977
  • The choice of control method and circuit must be decided after a broad inspection with the characteristics of load and control elements as well as that of electric and mechanical nature. In the present study, Pulse width modulated(PWM) SCR chopper was chosen and for the electric commutation, Jones' forced method was taken bacause of its having enough reverse bias energy. Objectives of experimentation by this system are; 1) the condition of SCR as a gate trigger pulse. 2) the observation of phenomena at the time of forced commutation 3) the experimentation on characteristics of speed control by PWM chopper. Above experimentation shows good characteristics, however, in the limit of narrow gap between the ON and OFF pulses, a complete control was not possible. So, that must be the point to be studied further alone with the harmonics influence.

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Effects of $SiO_2$ or SiON tunneling gate oxide on Au nano-particles floating gate memory (Au 나노 입자를 이용한 floating gate memory에서 $SiO_2$ or SiON 터널링 게이트 산화막의 영향)

  • Koo, Hyun-Mo;Lee, Woo-Hyun;Cho, Won-Ju;Koo, Sang-Mo;Chung, Hong-Bay;Lee, Dong-Uk;Kim, Jae-Hoon;Lee, Min-Seung;Kim, Eun-Kyu
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.67-68
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    • 2006
  • Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.

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Analysis of Phase Noise of High Stable Microwave Phased Locked Oscillator with Gate Voltage Tunning (게이트 전압 제어에 의한 마이크로파 고안정 위상동기발진기의 위상잡음 특성 분석)

  • 김성용;이영철
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.5
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    • pp.863-871
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    • 2003
  • In this paper, we design a high stable Ku-band phase-locked dielectric resonant microwave oscillator with the gate voltage controls of p-HEMT. By adapting the nonlinear equivalent elements which affects phase noise of microwave oscillator, we optimize the nonlinear elements of p-HEMT to have low phase noise operation. Using the scattering parameters according to bias voltages, we designed the gate voltage control microwave dielectric resonant oscillator and phase-locked loop circuits is applied to have the high stable operations. Designed microwave oscillator as a local oscillator of digital microwave communication shows that output power is 9.17dBm at 10.75GHz and it's phase noise is -88dBc/Hz at 10KHz offset frequency.

High Isolation and Linearity MMIC SPDT Switch for Dual Band Wireless LAN Applications (이중대역 무선랜 응용을 위한 높은 격리도와 선형성을 갖는 MMIC SPDT 스위치)

  • Lee, Kang-Ho;Koo, Kyung-Heon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.1 s.343
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    • pp.143-148
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    • 2006
  • This paper presents a high isolation and power-handling single-pole double-throw(SPDT) switch for dual band wireless LAN applications. The switch circuit has asymmetric topology which uses stacked-gate to have high power-handling and isolation for the Tx path. The proposed SPDT switch has been designed with optimum gate-width, bias, and number of stacked-gate FET. This SPDT switch has been implemented with $0.25{\mu}m$ GaAs pHEMT process which has Gmmax of 500mS/mm and fmax of 150GHz. The designed SPDT switch has the measured insertion loss of better than 0.9dB and isolation of better than 40dB for the Tx path and 25dB for the Rx path and the high power handling capability with PldB of about 23dBm for control voltage of -3/0V. The fabricated SPDT switch chip size is $1.8mm{\times}1.8mm$.

The Effects of Doping Hafnium on Device Characteristics of $SnO_2$ Thin-film Transistors

  • Sin, Sae-Yeong;Mun, Yeon-Geon;Kim, Ung-Seon;Park, Jong-Wan
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.199-199
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    • 2011
  • Recently, Thin film transistors (TFTs) with amorphous oxide semiconductors (AOSs) can offer an important aspect for next generation displays with high mobility. Several oxide semiconductor such as ZnO, $SnO_2$ and InGaZnO have been extensively researched. Especially, as a well-known binary metal oxide, tin oxide ($SnO_2$), usually acts as n-type semiconductor with a wide band gap of 3.6eV. Over the past several decades intensive research activities have been conducted on $SnO_2$ in the bulk, thin film and nanostructure forms due to its interesting electrical properties making it a promising material for applications in solar cells, flat panel displays, and light emitting devices. But, its application to the active channel of TFTs have been limited due to the difficulties in controlling the electron density and n-type of operation with depletion mode. In this study, we fabricated staggered bottom-gate structure $SnO_2$-TFTs and patterned channel layer used a shadow mask. Then we compare to the performance intrinsic $SnO_2$-TFTs and doping hafnium $SnO_2$-TFTs. As a result, we suggest that can be control the defect formation of $SnO_2$-TFTs by doping hafnium. The hafnium element into the $SnO_2$ thin-films maybe acts to control the carrier concentration by suppressing carrier generation via oxygen vacancy formation. Furthermore, it can be also control the mobility. And bias stability of $SnO_2$-TFTs is improvement using doping hafnium. Enhancement of device stability was attributed to the reduced defect in channel layer or interface. In order to verify this effect, we employed to measure activation energy that can be explained by the thermal activation process of the subthreshold drain current.

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Design of an Analog Array using Enhancement of Electric Field on Floating Gate MOSFETs (부유게이트에 지역전계강화 효과를 이용한 아날로그 어레이 설계)

  • Chai, Yong-Yoong
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.8
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    • pp.1227-1234
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    • 2013
  • An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

Etching characteristics of Al-Nd alloy thin films using magnetized inductively coupled plasma

  • Lee, Y.J.;Han, H.R.;Yeom, G.Y.
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 1999.10a
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    • pp.56-56
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    • 1999
  • For advanced TFT-LCD manufacturing processes, dry etching of thin-film layers(a-Si, $SiN_x$, SID & gate electrodes, ITO etc.) is increasingly preferred instead of conventional wet etching processes. To dry etch Al gate electrode which is advantageous for reducing propagation delay time of scan signals, high etch rate, slope angle control, and etch uniformity are required. For the Al gate electrode, some metals such as Ti and Nd are added in Al to prevent hillocks during post-annealing processes in addition to gaining low-resistivity($<10u{\Omega}{\cdot}cm$), high performance to heat tolerance and corrosion tolerance of Al thin films. In the case of AI-Nd alloy films, however, low etch rate and poor selectivity over photoresist are remained as a problem. In this study, to enhance the etch rates together with etch uniformity of AI-Nd alloys, magnetized inductively coupled plasma(MICP) have been used instead of conventional ICP and the effects of various magnets and processes conditions have been studied. MICP was consisted of fourteen pairs of permanent magnets arranged along the inside of chamber wall and also a Helmholtz type axial electromagnets was located outside the chamber. Gas combinations of $Cl_2,{\;}BCl_3$, and HBr were used with pressures between 5mTorr and 30mTorr, rf-bias voltages from -50Vto -200V, and inductive powers from 400W to 800W. In the case of $Cl_2/BCl_3$ plasma chemistry, the etch rate of AI-Nd films and etch selectivity over photoresist increased with $BCl_3$ rich etch chemistries for both with and without the magnets. The highest etch rate of $1,000{\AA}/min$, however, could be obtained with the magnets(both the multi-dipole magnets and the electromagnets). Under an optimized electromagnetic strength, etch uniformity of less than 5% also could be obtained under the above conditions.

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Highly Linear and Efficient Microwave GaN HEMT Doherty Amplifier for WCDMA

  • Lee, Yong-Sub;Lee, Mun-Woo;Jeong, Yoon-Ha
    • ETRI Journal
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    • v.30 no.1
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    • pp.158-160
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    • 2008
  • A highly linear and efficient GaN HEMT Doherty amplifier for wideband code division multiple access (WCDMA) repeaters is presented. For better performance, the adaptive gate bias control of the peaking amplifier using the power tracking circuit and the shunt capacitors is employed. The measured one-carrier WCDMA results show an adjacent channel leakage ratio of -43.2 dBc at ${\pm}2.5$-MHz offset with a power added efficiency of 40.1% at an average output power of 37 dBm, which is a 7.5 dB back-off power from the saturated output power.

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A Study On the Retention Time Distribution with Plasma Damage Effect

  • Yi Jae Young;Szirmay Laszlo;Yi Cheon Hee
    • Proceedings of the IEEK Conference
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    • 2004.08c
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    • pp.460-462
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    • 2004
  • The control of the data retention time is a main issue for realizing future high density dynamic random access memory. There are several leakage current mechanisms in which the stored data disappears. The mechanisms of data disappear is as follow, 1 )Junction leakage current between the junction, 2) Junction leakage current from the capacitor node contact, 3)Sub-threshold leakage current if the transfer transistor is affected by gate etch damage etc. In this paper we showed the plasma edge damage effect to find out data retention time effectiveness. First we measured the transistor characteristics of forward and reverse bias. And junction leakage characteristics are measured with/without plasma damage by HP4145. Finally, we showed the comparison TRET with etch damage, damage_cure_RTP and hydrogen_treatment. As a result, hydrogen_treatment is superior than any other method in a curing plasma etch damage side.

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