• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.41-47
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• 2022

Ag sintering technologies have received great attention as it was applied to the inverter of Tesla's electric vehicle Model III. Ag sinter bonding technology has advantages in heat dissipation design as well as high-temperature stability due to the intrinsic properties of the material, so it is useful for practical use of SiC and GaN devices. This study was carried out to understand the sinter joining temperature effect on the robust Ag sintered joints in air without pressure within 10 min. Electroplated Ag finished Cu dies (3 mm × 3 mm × 2 mm) and substrates (10 mm × 10 mm × 2 mm) were introduced, respectively, and nano Ag paste was applied as a bonding material. The sinter joining process was performed without pressure in air with the bonding temperature as a variable of 175 ℃, 200 ℃, 225 ℃, and 250 ℃. As results, the bonding temperature of 175 ℃ caused 13.21 MPa of die shear strength, and when the bonding temperature was raised to 200 ℃, the bonding strength increased by 157% to 33.99 MPa. When the bonding temperature was increased to 225 ℃, the bonding strength of 46.54 MPa increased by about 37% compared to that of 200 ℃, and even at a bonding temperature of 250 ℃, the bonding strength exceeded 50 MPa. The bonding strength of Ag sinter joints was directly influenced by changes in the necking thickness and interfacial connection ratio. In addition, developments in the morphologies of the joint interface and porous structure have a significant effect on displacement. This study is systematically discussed on the relationship between processing temperatures and bonding strength of Ag sinter joints.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• Korean Journal of Materials Research
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• v.32 no.6
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• pp.293-300
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• 2022

This study investigated a graded-refractive-index (GRIN) coating pattern capable of improving the light extraction efficiency of GaN light-emitting diodes (LEDs). The planar LEDs had total internal reflection thanks to the large difference in refractive index between the LED semiconductor and the surrounding medium (air). The main goal of this paper was to reduce the trapped light inside the LED by controlling the refractive index using various compositions of (TiO₂)_x(SiO₂)_1-x in GRIN LEDs consisting of five dielectric layers. Several types of multilayer LEDs were simulated and it was determined the transmittance value of the LEDs with many layers was greater than the LEDs with less layers. Then, the specific ranges of incident angles of the individual layers which depend on the refractive index were evaluated. According to theoretical calculations, the light extraction efficiency (LEE) of the five-layer GRIN is 25.29 %, 28.54 % and 30.22 %, respectively. Consequently, the five-layer GRIN LEDs patterned enhancement outcome LEE over the reference planar LEDs. The results suggest the increased light extraction efficiency is related to the loss of Fresnel transmission and the release of the light mode trapped inside the LED chip by the graded-refractive-index.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.121-121
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• 2010

ZnO is a promising material for the application of high efficiency light emitting diodes with short wavelength region for its large bandgap energy of 3.37 eV which is similar to GaN (3.39 eV) at room temperature. The large exciton binding energy of 60 meV in ZnO provide provides higher efficiency of emission for optoelectronic device applications. Several ZnO/ZnMgO multiple quantum well (MQW) structures have been grown on various substrates such as sapphire, GaN, Si, and so on. However, the achievement of high quality ZnO/ZnMgO MQW structures has been somehow limited by the use of lattice-mismatched substrates. Therefore, we propose the optical properties of ZnO/ZnMgO multiple quantum well (MQW) structures with different well widths grown on lattice-matched ZnO substrates by molecular beam epitaxy. Photoluminescence (PL) spectra show MQW emissions at 3.387 and 3.369 eV for the ZnO/ZnMgO MQW samples with well widths of 2 and 5 nm, respectively, due to the quantum confinement effect. Time-resolved PL results show an efficient photo-generated carrier transfer from the barrier to the MQWs, which leads to an increased intensity ratio of the well to barrier emissions for the ZnO/ZnMgO MQW sample with the wider width. From the power-dependent PL spectra, we observed no PL peak shift of MQW emission in both samples, indicating a negligible built-in electric field effect in the ZnO/$Zn_{0.9}Mg_{0.1}O$ MQWs grown on lattice-matched ZnO substrates.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.180-180
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• 2010

Thin film transistors (TFTs) based on oxide semiconductors have emerged as a promising technology, particularly for active-matrix TFT-based backplanes. Currently, an amorphous oxide semiconductor, such as InGaZnO, has been adopted as the channel layer due to its higher electron mobility. However, accurate and repeatable control of this complex material in mass production is not easy. Therefore, simpler polycrystalline materials, such as ZnO and $SnO_2$, remain possible candidates as the channel layer. Inparticular, ZnO-based TFTs have attracted considerable attention, because of their superior properties that include wide bandgap (3.37eV), transparency, and high field effect mobility when compared with conventional amorphous silicon and polycrystalline silicon TFTs. There are some technical challenges to overcome to achieve manufacturability of ZnO-based TFTs. One of the problems, the stability of ZnO-based TFTs, is as yet unsolved since ZnO-based TFTs usually contain defects in the ZnO channel layer and deep level defects in the channel/dielectric interface that cause problems in device operation. The quality of the interface between the channel and dielectric plays a crucial role in transistor performance, and several insulators have been reported that reduce the number of defects in the channel and the interfacial charge trap defects. Additionally, ZnO TFTs using a high quality interface fabricated by a two step atomic layer deposition (ALD) process showed improvement in device performance In this study, we report the fabrication of high performance ZnO TFTs with a $Si_3N_4$ gate insulator treated using plasma. The interface treatment using electron cyclotron resonance (ECR) $O_2$ plasma improves the interface quality by lowering the interface trap density. This process can be easily adapted for industrial applications because the device structure and fabrication process in this paper are compatible with those of a-Si TFTs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.371-375
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• 2019

Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a $SiO_2/Si_3N_4$ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.18 no.5
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• pp.217-224
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• 2008

A stoichiometric mixture of evaporating materials for $ZnIn_2Se_4$ single crystal thin films was prepared from horizontal electric furnace. To obtain the single crystal thin films, $ZnIn_2Se_4$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by the Hot Wall Epitaxy (HWE) system. The source and substrate temperatures were $630^{\circ}C$ and $400^{\circ}C$, respectively. The crystalline structure of the single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction (DCXD). The carrier density and mobility of $ZnIn_2Se_4$ single crystal thin films measured from Hall effect by van der Pauw method are $9.41\times10^{16}cm^{-3}$ and $292cm^2/v{\cdot}s$ at 293 K, respectively. The temperature dependence of the energy band gap of the $ZnIn_2Se_4$ obtained from the absorption spectra was well described by the Varshni's relation, $E_g(T)=1.8622eV-(5.23\times10^{-4}eV/K)T^2/(T+775.5K)$. The crystal field and the spin-orbit splitting energies for the valence band of the $ZnIn_2Se_4$ have been estimated to be 182.7 meV and 42.6 meV, respectively, by means of the photocurrent spectra and the Hopfield quasicubic model. These results indicate that the splitting of the ${\Delta}so$ definitely exists in the ${\Gamma}_5$ states of the valence band of the $ZnIn_2Se_4/GaAs$ epilayer. The three photo current peaks observed at 10 K are ascribed to the $A_{1}-$, $B_{1}-exciton$ for n = 1 and $C_{27}-exciton$ peaks for n = 27.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.309-318
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• 2002

A stoichiometric mixture of evaporating materials for $CdIn_2S_4$ single crystal thin films was prepared from horizontal electric furnace. To obtain the single crystal thin films, $CdIn_2S_4$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by the Hot Wall Epitaxy (HWE) system. The source and substrate temperatures were $630^{\circ}C$ and $420^{\circ}C$, respectively. The crystalline structure of the single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction (DCXD). The carrier density and mobility of $CdIn_2S_4$ single crystal thin films measured with Hall effect by van der Pauw method are $9.01{\times}10^{16}\;cm^{-3}$ and $219\;cm^2/V{\cdot}s$ at 293 K, respectively. The temperature dependence of the energy band gap of the $CdIn_2S_4$ obtained from the absorption spectra was well described by the Varshni's relation, $E_g(T)=2.7116\;eV-(7.74{\times}10^{-4}\;eV)T^2/(T+434)$. The crystal field and the spin-orbit splitting energies for the valence band of the $CdIn_2S_4$ have been estimated to be 0.1291 eV and 0.0248 eV, respectively, by means of the photocurrent spectra and the Hopfield quasi cubic model. These results indicate that the splitting of the ${\Delta}so$ definitely exists in the ${\Gamma}5$ states of the valence band of the $AgInS_2$/GaAs epilayer. The three photocurrent peaks observed at 10K areascribed to the $A_1$-, $B_1$-, and C1-exciton peaks for n = 1.

• Tribology and Lubricants
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• v.35 no.5
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• pp.274-285
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• 2019

Chemical mechanical polishing (CMP), which is a material removal process involving chemical surface reactions and mechanical abrasive action, is an essential manufacturing process for obtaining high-quality semiconductor surfaces with ultrahigh precision features. Recent rapid growth in the industries of digital devices and semiconductors has accelerated the demands for processing of various substrate and film materials. In addition, to solve many issues and challenges related to high integration such as micro-defects, non-uniformity, and post-process cleaning, it has become increasingly necessary to approach and understand the processing mechanisms for various substrate materials and abrasive particle behaviors from a tribological point of view. Based on these backgrounds, we review recent CMP R&D trends in this study. We examine experimental and analytical studies with a focus on substrate materials and abrasive particles. For the reduction of micro-scratch generation, understanding the correlation between friction and the generation mechanism by abrasive particle behaviors is critical. Furthermore, the contact stiffness at the wafer-particle (slurry)-pad interface should be carefully considered. Regarding substrate materials, recent research trends and technologies have been introduced that focus on sapphire (${\alpha}$-alumina, $Al_2O_3$), silicon carbide (SiC), and gallium nitride (GaN), which are used for organic light emitting devices. High-speed processing technology that does not generate surface defects should be developed for low-cost production of various substrates. For this purpose, effective methods for reducing and removing surface residues and deformed layers should be explored through tribological approaches. Finally, we present future challenges and issues related to the CMP process from a tribological perspective.