• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.48-48
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• 2007

P-type transparent conducting $CuGaO_2$ thin films have been prepared by DC/RF sputtering using Quartz(0001) and sapphire(0001) substrates. The target was fabricated by heating a stoichiometric mixture of CuO and $Ga_2O_3$ at 1373K for 12h under $N_2$ atmosphere. The film were deposited under mixture gas of Ar and $O_2(Ar:O_2=4:1)$ during 10~30min. and the as-deposited films were annealed at 1123K and $N_2$ atmosphere. Room temperature conductivity and the activation energy of the sintered body in the temperature range of 223K ~ 423K were 0 004S/cm, 1.9eV, respectively. XRD revealed that all of the as-deposited films were amorphous. Heating of the films deposited on Quartz substrates above 1123K resulted in crystallization with a second phase of $CuSiO_3$, which was assumed owing to reaction with Quartz substrate. The single phase of $CuGaO_2$ was obtained at the film deposited on the sapphire substrates. The transmittance after annealing of DC- and RF-sputtered films were 55~75% at 550nm. From the transmittance and reflectance measurement. the direct band gap of the DC/RF-sputtered films were 3.63eV and 3.57eV. and there was little difference between DC and RF sputtered films.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.44-44
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• 2009

Recently, transparent ZnO-based TFTs have attracted much attention for flexible displays because they can be fabricated on plastic substrates at low temperature. We report the fabrication and characteristics of ZnO channel layers(ZnO TFTs) having different channel thicknesses. The ZnO film were deposited as active channel layers on $Si_3N_4/Ti/SiO_2p$-Si substrates by rf magnetron sputtering at $100\;^{\circ}C$ without additional annealing. Also the Zno thin films deposited at oxygen partial pressures of 40%. ZnO TFTs using a bottom-gate configuration were investigated. The $Si_3N_4$ film were deposited as gate insulator by PE-CVD at $15\;^{\circ}C$. All Processes were processed below $150^{\circ}C$ which is optimal temperature for flexible display and were used dry etching method.

• Korean Journal of Materials Research
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• v.28 no.11
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• pp.659-662
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• 2018

We report the properties of infrared photodetectors based on two kinds of quantum dots(QDs): i) 2.0 ML InAs QDs by the Stranski-Krastanov growth mode(SK QDs) and ii) sub-monolayer QDs by $4{\times}[0.3ML/1nm\;In_{0.15}Ga_{0.85}As]$ deposition(SML QDs). The QD infrared photodetector(QDIP) structure of $n^+-n^-(QDs)-n^+$ is epitaxially grown on GaAs (100) wafers using molecular-beam epitaxy. Both the bottom and top contact GaAs layers are Si doped at $2{\times}10^{18}/cm^3$. The QD layers are grown with Si doping of $2{\times}10^{17}/cm^3$ and capped by an $In_{0.15}Ga_{0.85}As$ layer at $495^{\circ}C$. The photoluminescence peak(1.24 eV) of the SML QDIP is blue-shifted with respect to that (1.04 eV) of SK QDIPs, suggesting that the electron ground state of SML QDIP is higher than that of the SK QDIP. As a result, the photoresponse regime(${\sim}9-14{\mu}m$) of the SML QDIP is longer than that (${\sim}6-12{\mu}m$) of the SK QDIP. The dark current of the SML QDIP is two orders of magnitude smaller value than that of the SK QDIP because of the inserted $Al_{0.08}Ga_{0.92}As$ layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.12
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• pp.1009-1014
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• 2012

Hydrogenated amorphous silicon (${\alpha}$-Si:H) layers deposited by plasma enhanced chemical vapor deposition (PECVD) are investigated for use in silicon hetero-junction solar cells employing n-type crystalline silicon (c-Si) substrates. The optical and structural properties of silicon hetero-junction devices have been characterized using spectroscopy ellipsometry and high resolution cross-sectional transmission electron micrograph (HRTEM). In addition, the effective carrier lifetime is measured by the quasi-steady-state photocoductance (QSSPC) method. We have studied on the correlation between the order of ${\alpha}$-Si:H and the passivation quality at the interface of ${\alpha}$-Si:H/c-Si. Base on the result, we have fabricated a silicon hetero-junction solar cell incorporating the ${\alpha}$-Si:H passivation layer with on open circuit voltage ($V_{oc}$) of 637 mV.

• Korean Journal of Materials Research
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• v.14 no.2
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• pp.133-140
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• 2004

We carried out anodic aluminum oxide (AAO) on a Si and a sapphire substrate. For anodic oxidation of Al two types of specimens prepared were Al(0.5 $\mu\textrm{m}$)!Si and Al(0.5 $\mu\textrm{m}$)/Ti(0.1 $\mu\textrm{m}$)$SiO_2$(0.1 $\mu\textrm{m}$)/GaN(2 $\mu\textrm{m}$)/Sapphire. Surface morphology of Al film was analyzed depending on the deposition methods such as sputtering, thermal evaporation, and electron beam evaporation. Without conventional electron lithography, we obtained ordered nano-pattern of porous alumina by in- situ process. Electropolishing of Al layer was carried out to improve the surface morphology and evaluated. Two step anodizing was adopted for ordered regular array of AAO formation. The applied electric voltage was 40 V and oxalic acid was used as an electrolyte. The reference electrode was graphite. Through the optimization of process parameters such as electrolyte concentration, temperature, and process time, a regular array of AAO was formed on Si and sapphire substrate. In case of Si substrate the diameter of pore and distance between pores was 50 and 100 nm, respectively. In case of sapphire substrate, the diameter of pore and distance between pores was 40 and 80 nm, respectively

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.206-206
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• 2010

본 연구에서는 신경망을 이용하여 SiN 박막의 특성을 예측하는 모델을 개발하였다. 신경망으로는 일반화된 회귀 신경망 (generalized regression neural network-GRNN)을 이용하였고, GRNN 모델의 예측수행은 유전자 알고리즘 (genetic algorithm-GA)을 이용하여 최적화 하였다. 개발된 모델을 이용하여 증착률과 굴절률 및 균일도를 공정변수의 함수로 예측하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.359-359
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• 2014

In this study, surface plasmon resonance structures for the selective and the enhanced transmission of infrared light were designed. In order to relieve the large discontinuity of refractive index between air and metal hole array, $Si_3N_4$ was used as the impedance matching layer. Experimental parameter were calculated and determined in advance by the rigorous coupled wave analysis (RCWA) simulation, and then the experiment was carried out. A 2-dimensional metal hole array structures were patterned on the size of $1{\times}1cm^2$ GaAs substrate using photolithography process, and 5 nm thick Ti, 50 nm thick Au were deposited by E-beam evaporator, respectively. Subsequently, $Si_3N_4$ films with various thicknesses (150, 350, 550, and 750 nm) were deposited by plasma enhanced chemical vapor deposition (PECVD). For the comparison, transmittance of specimens with and without $Si_3N_4$ was measured using Fourier transform infrared spectroscopy (FTIR) in the range of $2.5-15{\mu}m$. Furthermore, the surface and the cross-sectional images were collected from the specimens by scanning electron microscopy (SEM). From the results, it was demonstrated that the transmittance was enhanced up to 80% by the deposition of 750 nm $Si_3N_4$ at $6.23{\mu}m$. It has advantage of enhanced transmission despite the simple fabrication process.

• Electrical & Electronic Materials
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• v.10 no.7
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• pp.692-699
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• 1997

The silicon doped $Al_{0.33}$G $a_{0.67}$As were grown by molecular beam epitaxy. The electroreflectance(ER) spectra of Schottky barrier Au/n-Al/suu x/G $a_{1-x}$ As have been measured at various modulation voltage( $V_{ac}$ ) and dc bias voltage( $V_{bias}$). From the observed Franz-Keldysh oscillations(FKO) peak, the band gap energy of the $Al_{x}$G $a_{1-x}$ As is 1.91 eV which corresponds to an Al composition of 33%. The internal electric field( $E_{i}$)of this sample is 2.96$\times$10$^{5}$ V/cm. As the modulation voltage( $V_{ac}$ ) is changed, the line shape of ER signal does not change but its amplitude varies linearly. The amplitude as a function of modulation voltage has saturated at 0.8 V. The internal electric field has decreased from 6.47$\times$10$^{5}$ V/cm to 2.00$\times$10$^{5}$ V/cm as the dc bias voltage( $V_{bias}$) increases from -3.5 V to +0.8 V. The values of built-in voltage( $V_{bi}$ ) and carrier concentration(N) determined from the plot of $V_{bias}$ from the plot of $V_{bias}$ versus $E_{i}$$^{2}$ are 0.855 V and 3.83$\times$10$^{17}$ c $m^{-3}$ , respectively.ively.y.y.y.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.327.1-327.1
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• 2014

Nitrides-on-silicon structures are considered to be an excellent candidate for unique design architectures and creating devices for high-power applications. Therefore, a lot of effort has been concentrating on growing high-quality III-nitrides on Si substrates, mostly Si(111) and Si(001) substrates. However, there are several fundamental problems in the growth of nitride compound semiconductors on silicon. First, the large difference in lattice constants and thermal expansion coefficients will lead to misfit dislocation and stress in the epitaxial films. Second, the growth of polar compounds on a non-polar substrate can lead to antiphase domains or other defective structures. Even though the lattice mismatches are reached to 16.9 % to GaN and 19 % to AlN and a number of dislocations are originated, Si(111) has been selected as the substrate for the epitaxial growth of nitrides because it is always favored due to its three-fold symmetry at the surface, which gives a good rotational matching for the six-fold symmetry of the wurtzite structure of nitrides. Also, Si(001) has been used for the growth of nitrides due to a possible integration of nitride devices with silicon technology despite a four-fold symmetry and a surface reconstruction. Moreover, Si(110), one of surface orientations used in the silicon technology, begins to attract attention as a substrate for the epitaxial growth of nitrides due to an interesting interface structure. In this system, the close lattice match along the [-1100]AlN/[001]Si direction promotes the faster growth along a particular crystal orientation. However, there are insufficient until now on the studies for the growth of nitride compound semiconductors on Si(110) substrate from a microstructural point of view. In this work, the microstructural properties of nitride thin layers grown on Si(110) have been characterized using various TEM techniques. The main purpose of this study was to understand the atomic structure and the strain behavior of III-nitrides grown on Si(110) substrate by molecular beam epitaxy (MBE). Insight gained at the microscopic level regarding how thin layer grows at the interface is essential for the growth of high quality thin films for various applications.