• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.569-577
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• 1999

A wideband RF receiver for satellite mobile communications system was fabricated and evaluated of performance in low noise amplifier and high gain amplifier. The low noise amplifier used to the resistive decoupling and self-bias circuits. The low noise amplifier is fabricated with both the RF circuits and the self-bias circuits. Using a INA-03184, the high gain amplifier consists of matched amplifier type. The active bias circuitry can be used to provide temperature stability without requiring the large voltage drop or relatively high-dissipated power needed with a bias stabilized resistor. The bandpass filter was used to reduce a spurious level. As a result, the characteristics of the receiver implemented here show more than 55 dB in gain, 50.83 dBc in a spurious level and less than 1.8 : 1 in input and output voltage standing wave ratio(VSWR), especially the carrier to noise ratio is a 43.15 dB/Hz at a 1 KHz from 1537.5 MHz.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.184-184
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• 2011

반도체 전자 소자의 초고집적회로(VLSI, Very Large Scale Integrated Circuit)가 수년간 지속됨에 따라 실리콘 기반으로 하는 MOSFET 성능의 한계에 도달하게 되었다. 재료 물성, 축소, 소자 공정 등에 대한 원인으로 이를 극복하고자 하는 재료와 성능향상에 관한 연구가 진행되고 있다. 이에 기존 시스템의 전자의 전하 정보만을 응용하는 것이 아니라 전자의 스핀 정보까지 고려하는 스핀트로닉스 연구분야가 주목을 받고 있다. Spin-FET는 스핀 주입, 스핀 조절, 스핀측정 등으로 나뉘어 연구되고 있으며 이 중 스핀 주입의 효율 향상이 우선시 해결되어야 한다. 일반적으로 스핀 주입 과정에서 소스가 되는 강자성체와 스핀 확산 거리가 긴 반도체 물질과의 Conductance mismatch가 문제되고 있다. 이에 자성 반도체는 근본적인 문제를 해결하고 반도체와 자성체의 특성을 동시에 나타내는 물질로써, Si과 Ge (4족) 등의 반도체뿐만 아니라, GaAs, InP (3-5족), ZnO, ZnTe (2-6족) 등의 반도체 또한 많은 연구가 이루어지고 있다. 자성 반도체에서 해결해야 할 가장 큰 문제는 물질이 자성을 잃는 Curie 온도를 상온 이상으로 높이는 것이다. 이에 본 연구는 전이금속이 도핑된 4족 Si 반도체 박막을 성장하고 후처리 공정을 통하여 나타나는 구조적, 자기적 특성을 연구하였다. 펄스 레이저 증착 방법을 통하여 p-type Si 기판위에 전이금속 Fe이 도핑된 박막을 500 nm 로 성장하였다. 성장 온도는 $250^{\circ}C$로 하였고, 성장 분압은 $3 {\times}10^{-3}$Torr 로 유지하며 $N_2$ 가스를 사용하였다. 구조적 결과를 보기 위해 X선 회절 분석과 원자력 현미경 결과를 확인하였고, 자기적 특성을 확인하기 위해 저온에서 초전도 양자 간섭계로 조사하였다. XRD를 통해 (002)면, (004)면의 Si 기판 결정을 보았으며, Fe 관련된 이차상이 형성됨을 예측해 보았다. ($Fe_3Si$, $Fe_2Si$ 등) 초전도 양자 간섭계에서 20 K에서 측정한 이력 현상을 관찰하고, 온도변화에 따른 전체 자기모멘트를 관찰하였으며 이는 상온에서도 강자성 특성이 나타남을 확인하였다.

• Journal of Broadcast Engineering
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• v.18 no.6
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• pp.884-894
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• 2013

In this paper, we investigate the characteristics of power amplifiers and simplified memoryless non-linear power amplifier models for energy efficient communication system. First, we present the transfer function of GaAs FET (Gallium Arsenide Field Effect Transistor) that is widely used for high power amplifier. From those investigations, we introduce the instantaneous efficiencies and methods of amplification by assuming that the saturated current is constant, while perfect linearity is exploited under knee voltage. Then, we discuss four non-linear power amplifier models in a baseband signal processing. Finally, we explain the specified total power consumption model in a base station to achieve the resonable analysis for energy efficient communication.