• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.452-456
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• 2010

Multiplication is a fundamental arithmetic operation in many digital signal processing (DSP) and communication algorithms. The group CSD (GCSD) multiplier was recently proposed based on the variation of canonical signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In this paper, it is shown that, by exploiting the characteristics of the filter coefficients, GCSD multipliers can be used for the efficient implementation of time-multiplexed FIR filters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.33-38
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• 2009

The group CSD (GCSD) multiplier was recently proposed based on the variation of canonic signed digit (CSD) encoding and partial product sharing. This multiplier provides an efficient design when the multiplications are performed only with a few predetermined coefficients (e.g., FFT). In many DSP applications such as FFT, the (2W-1)-bit product obtained from W-bit multiplicand and W-bit multiplier is quantized to W-bits by eliminating the (W-1) least-significant bits. This paper presents an error compensation method for a fixed-width GCSD multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, the encoded signals from the GCSD multiplier are used for the generation of error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 79% reduction in area compared with the fixed-width modified Booth multiplier.