• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 추계학술대회 논문집 전기물성,응용부문
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• pp.57-58
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• 2006

As the power density and switching frequency increase, thermal analysis of power electronics system becomes imperative. The analysis provides valuable information on the semiconductor rating, long-term reliability. In this paper, thermal distribution of the Non Punchthrough(NPT) Insulated Gate Bipolar Transistor has been studied. For analysis of thermal distribution, we obtained results by using finite element simulator, Ansys and thermal distributions form experiments.

• 전기전자학회논문지
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• 제22권2호
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• pp.488-490
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• 2018

본 연구에서는 급격한 스위칭 특성을 달성하기 위해 싱글단일-게이트 실리콘 채널에서 전하 캐리어의 양의 피드백을 이용하는 새롭게 설계된 피드백 전계 효과 트랜지스터를 제안한다. 에너지 밴드 다이어그램, I-V 특성, 문턱전압 기울기 및 on/off 전류 비는 TCAD 시뮬레이터를 이용하여 분석한다. 피드백 전계 효과 트랜지스터의 중요한 특징 중 하나인 히스테리시스의 특성을 보기 위해 게이트 절연막 물질과 게이트 전극물질을 변경하여 시뮬레이션을 진행했다. 이러한 특성변화는 피드백 전계효과 트랜지스터의 문턱전압 ($V_{TH}$)을 변화시켰고, 메모리 윈도우 폭이 작아지는 현상을 보였다.

• 전기전자학회논문지
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• 제22권2호
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• pp.339-343
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• 2018

본 연구는 IGBT 구조에서 JFET 영역의 드라이브 인 확산거리 및 JFET영역의 윈도우의 크기에 따라서 항복전압과 온상태 전압강하 특성을 분석하였다. 시간은 동일하게 하면서 온도를 상승시켜 확산거리를 조정하였으며, 그 결과 항복전압은 감소되나, 온 상태 전압 강하 특성은 현저하게 좋아지는 것을 알 수 있었다. 따라서 드리프트 층의 비저항을 변화시켜 항복전압을 1440V로 고정하여 1.15V의 낮은 온 상태 전압 강하 값을 얻을 수 있었다. 따라서 본 연구결과를 토대로 Planar Gate IGBT에서는 JFET 영역의 공정 및 설계 파라미터를 효율적으로 조절한다면 같은 항복전압을 기준으로 상당히 낮은 온 상태 전압 강하 값을 확보할 수 있어, 소비전력의 측면에서 충분히 활용할 수 있을 것으로 판단된다.

• 반도체디스플레이기술학회지
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• 제10권1호
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• pp.63-73
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• 2011

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with conventional pseudomorphic HEMTs (PHEMTs). For the optimized device design and development, we have performed the calibration on the DC characteristics of our fabricated 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure on the GaAs wafer using the hydrodynamic transport model of a commercial 2D ISE-DESSIS device simulator. The well-calibrated device simulation shows very good agreement with the DC characteristic of the 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.

• 한국자동차공학회논문집
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• 제23권1호
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• pp.25-33
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• 2015

This paper presents the d-q axis equivalent circuit model of an interior permanent magnet (IPM) which includes the iron loss resistance. The model is implemented to be able to run in real-time on the FPGA-based HIL simulator. Power electronic devices are removed from the motor control unit (MCU) and a separated controller is interfaced with the real-time simulated motor drive through a set of proper inputs and outputs. The inputs signals of the HIL simulation are the gate driver signals generated from the controller, and the outputs are the winding currents and resolver signals. This paper especially presents iron loss prediction which is introduced by means of comparing the torque calculated from d-q axis currents and the desired torque; and minimizing the torque difference. This prediction method has stable prediction algorithm to reduce torque difference at specific speed and load. Simulation results demonstrate the feasibility and effectiveness of the proposed methods.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• Nuclear Engineering and Technology
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• 제55권1호
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• pp.248-253
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• 2023

Directly, it is not possible to measure the absorbed dose of radiopharmaceuticals in the organs of the human body. Therefore, simulation methods are utilized to estimate the dose in distinct organs. In this study, individual organs were separately considered as the source organ or target organ to calculate the mean absorption dose, which SAF and S factors were then calculated according to the target uptake via MIRD method. Here, ^99mTc activity distribution within the target was analyzed using the definition and simulation of ideal organs by summing the fraction of cumulative activities of the heart as source organ. Thus, GATE code was utilized to simulate the Zubal humanoid phantom. To validate the outcomes in comparison to the similar results reported, the accumulation of activity in the main organs of the body was calculated at the moment of injection and cardiac rest condition after 60 min of injection. The results showed the highest dose absorbed into pancreas was about 21%, then gallbladder 18%, kidney 16%, spleen 15%, heart 8%, liver 8%, thyroid 7%, lungs 5% and brain 2%, respectively, after 1 h of injection. This distinct simulation model may also be used for different periods after injection and modifying the prescribed dose.

• 한국시뮬레이션학회논문지
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• 제9권4호
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• 대한전자공학회논문지SD
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• 제48권9호
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• pp.1-5
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• 2011

본 논문에서는 AlGaN/GaN HEMT의 DC 및 RF 특성을 최적화 하기위해서 2차원 소자 시뮬레이터를 이용하여 연구를 진행하였다. 먼저, AlGaN층의 두께, Al mole fraction 의 변화에 따른 2차원 전자가스 채널의 농도변화가 생기는 현상을 바탕으로 DC특성을 분석하였다. 다음 게이트, 소스, 드레인 전극의 크기와 위치 변화에 따른 RF 특성을 분석하였다. 그 결과 Al mole fraction이 0.2몰에서 0.45몰로 증가할수록 전달이득(transconductance, $g_m$) 과 I-V 특성이 향상됨을 확인하였다. 한편 AlGaN층의 두께가 10nm에서 50nm로 증가할수록 I-V특성은 향상되지만 $g_m$은 감소하는것을 확인하였다. RF 특성에서는 게이트 길이가 가장 큰 영향을 미치며 그 길이가 짧을수록 RF특성이 향상되는 것을 확인하였다.

• 대한전자공학회논문지SD
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• 제48권12호
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• pp.1-7
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• 2011

본 연구에서는 나노와이어 junctionless 트랜지스터의 문턱전압과 평탄전압을 위한 해석학적 모델링을 제시하였고 3차원 소자 시뮬레이션으로 검증하였다. 그리고 junctionless 트랜지스터의 소자설계 가이드라인을 설정하는 방법과 그 예를 제시하였다. 제시한 문턱전압과 평탄전압 모델은 3차원 시뮬레이션 결과와 잘 일치하였다. 나노와이어 반경과 게이트 산화층 두께가 클수록 또 채널 불순물 농도가 높을수록 문턱전압과 평탄전압은 감소하였다. 게이트 일함수와 원하는 구동전류/누설전류 비가 주어지면 나노와이어 반경, 게이트 산화층 두께, 채널 불순물 농도에 따른 junctionless 트랜지스터의 소자설계 가이드라인을 설정하였다. 나노와이어 반경이 작을수록 산화층의 두께가 얇을수록 채널 불순물 농도가 큰 소자를 설계할 수 있음을 알 수 있었다.