• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.2
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• pp.87-91
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• 2013

Carbon-nanotube field-effect transistors (CNFETs) have drawn wide attention as one of the potential substitutes for metal-oxide-semiconductor field-effect transistors (MOSFETs) in the sub-10-nm era. Output characteristics of coaxially gated CNFETs were simulated using FETToy simulator to reveal the dependence of drain current on the nanotube diameter and gate oxide thickness. Nanotube diameter and gate oxide thickness employed in the simulation were 1.5, 3, and 6 nm. Simulation results show that drain current becomes large as the diameter of nanotube increases or insulator thickness decreases, and nanotube diameter affects the drain current more than the insulator thickness. An equation relating drain saturation current with nanotube diameter and insulator thickness is also proposed.

• ETRI Journal
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• v.34 no.4
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• pp.633-636
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• 2012

A dynamic analysis of an amorphous silicon (a-Si) thin film transistor liquid crystal display (TFT-LCD) pixel is presented using new a-Si TFT and liquid crystal (LC) capacitance models for a Simulation Program with Integrated Circuit Emphasis (SPICE) simulator. This dynamic analysis will be useful when predicting the performance of LCDs. The a-Si TFT model is developed to accurately estimate a-Si TFT characteristics of a bias-dependent gate to source and gate to drain capacitance. Moreover, the LC capacitance model is developed using a simplified diode circuit model. It is possible to accurately predict TFT-LCD characteristics such as flicker phenomena when implementing the proposed simulation model.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.60-68
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• 1993

Thw VLSI device of submicron level trends to have a low level of reliability because of hot carriers which are caused by short channel effects and which do not appear in a long-channel MOSFET operated in 5V. In order to minimize the generation of hot carrier, much research has been made into various types of drain structures. This study has suggested CG MOSFET (Concaved Gate MOSFET) as new drain structure and compared its electrical characteristics with those of the conventional MOSFET and LDD-structured MOSFET by making use of a simulation method. These three device were assumed to be produced by the LOCOS process and a computer-based analysis(PISCES-2B simulator) was carried out to verify the hot electron-resistant behaviours of the devices. In the present simulation, the channel length of these devises was 1.0$\mu$m and their DC characteristics, such as VS1DT-IS1DT curves, gate and substrate current, potential contours, breakdown voltage and electric field were compared with one another.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.107-117
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• 2010

An analytical subthreshold swing model is presented for symmetric double-gate (DG) MOSFETs with Gaussian doping profile in vertical direction. The model is based on the effective conduction path effect (ECPE) concept of uniformly doped symmetric DG MOSFETs. The effect of channel doping on the subthreshold swing characteristics for non-uniformly doped device has been investigated. The model also includes the effect of various device parameters on the subthreshold swing characteristics of DG MOSFETs. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained by using the commercially available $ATLAS^{TM}$ device simulator. The model is believed to provide a better physical insight and understanding of DG MOSFET devices operating in the subthreshold regime.

• Transactions on Electrical and Electronic Materials
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• v.2 no.4
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• pp.30-32
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• 2001

In this paper, a new silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n$^{+}$ cathode region. The improvement of latch-up performance is verified using the two- dimensional simulator MEDICI and the simulation results on the latch-up current density are 4468 A/cm2 for the proposed LIGBT and 1343 A/$\textrm{cm}^2$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.T.

• Fire Science and Engineering
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• v.10 no.2
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• pp.28-39
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• 1996

A recently developed electro-thermal simulation methodology is used to analyze the behavior of a PWM(Pulse-Width-Modulated) voltage source inverter which uses IGBT(Insulated Gate Bipolar Transistor) as the switching devices. In the electro-thermal network simulation methdology, the simulator solves for the temperature distribution within the power semiconductor devices(IGBT electro-thermal model), control logic circuitry, the IGBT gate drivers, the thermal network component models for the power silicon chips, package, and heat sinks as well as the current and voltage within the electrical network. The thermal network describes the flow of heat form the chip surface through the package and heat sink and thus determines the evolution of the chip surface temperature used by the power semiconductor device models. The thermal component model for the device silicon chip, packages, and heat sink are developed by discretizing the nonlinear heat diffusion equation and are represented in component from so that the thermal component models for various package and heat sink can be readily connected to on another to form the thermal network.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.92-96
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• 1999

As CMOS technologies have been rapidly developed, bridging faults have been relatively increased. IDDQ testing is a current testing methodology which can enhance reliability of the circuit since it efficiently detects bridging faults that are difficult to detect by functional testing. In this paper we consider internal bridging faults occurred in each gate of logic circuits under test and finally develop a fault simulator for IDDQ testing to detect assumed bridging faults.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.232-235
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• 1995

To improve the DIBL characteristics of deep sub micron BC PMOSFETs, the methods of DCI(Deep Channel Implantation) and Hale Implantation have been reported. In this study, using the process simulator TSUPREM4, we simulated the 0.25$\mu\textrm{m}$ and 0.45$\mu\textrm{m}$ gate length BC PMOSFETs applying the both methods to improve the DIBL characteristics, and their electric characteristics were compared to find the mothod suitable far deep sub-half micron BC PMOSFETs, using the device simulator MEDICI. So we found out that the method of Halo Implantation could be applied to deep sub-half micron BC PMOSFETs for 255 Mbit DRAM.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.363-368
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• 2012

A feedwater controller targeted for an ABWR has been implemented using a modern field programmable gate array (FPGA), and verified using the full scope simulator at Taipower's Lungmen nuclear power station. The adopted control algorithm is a rule-based fuzzy logic. Point to point validation of the FPGA circuit board has been executed using a digital pattern generator. The simulation model of the simulator was employed for verification and validation of the controller design under various plant initial conditions. The transient response and the steady state tracking ability were evaluated and showed satisfactory results. The present work has demonstrated that the FPGA based approach incorporated with a rule-based fuzzy logic control algorithm is a flexible yet feasible approach for feedwater controller design in nuclear power plant applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.268-270
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• 2002

For analysis of semiconductor's electrons transmission characteristics, Impact ionization(I.I.) is very important. I.I. are generation process of electron-hole pairs. Therefore, the characteristics of device can change along with applied voltage or temperature. In this paper, we are scaled down the gate length to 50nm. Also, using TCAD simulator, we are analyzed I.I. and breakdown about three models-Van Overstraeten , Okuto and Ours models.