• Title/Summary/Keyword: GATE simulator

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Electrical Characteristics of the Dual Gate Emitter Switched Thyristor (Dual Gate Emitter Switched Thyristor의 전기적 특성)

  • Kim, Nam-Soo;Lee, Eung-Rae;Cui, Zhi-Yuan;Kim, Yeong-Seuk;Kim, Kyoung-Won;Ju, Byeong-Kwon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.5
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    • pp.401-406
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    • 2005
  • Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

Flood Response Disaster Prevention Facility Simulator Design and Prototype Development Using Spill and Inundation Model (유출·침수모델을 이용한 홍수대응 방재시설 시뮬레이터 설계 및 프로토타입 개발)

  • Seo, Sung Chul;Kim, Ui Hwan;Park, Hyung Keun
    • KSCE Journal of Civil and Environmental Engineering Research
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    • v.43 no.2
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    • pp.259-266
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    • 2023
  • Global climate change is increasing, and the damage and scale of localized torrential rains are increasing. Pre-flood analysis simulation results should be derived from rainfall data through rainfall forecasts to prevent flood damage. In addition, it is necessary to control the use and management of flood response disaster prevention facilities through immediate decision-making. However, methods using spills and flood models such as XPSWMM and GATE2018 are limited due to professional usability and complex analytical procedures. Prototype (flood disaster prevention facility simulator) of this study is developed by calculating rainfall (short-term and long-term) using CBD software development methods. It is also expected to construct administrator and user-centric interfaces and provide GIS and visible data (graphs, charts, etc.).

Development of FPGA Based HIL Simulator for PMS Performance Verification of Natural Liquefied Gas Carriers (액화천연가스운반선의 PMS 성능 검증을 위한 FPGA 기반 HIL 시뮬레이터 개발)

  • Lee, Kwangkook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.22 no.7
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    • pp.949-955
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    • 2018
  • Hardware-in-the-loop (HIL) simulation is a technique that can be employed for developing and testing complex real-time embedded systems. HIL simulation provides an effective platform for verifying power management system (PMS) performance of liquefied natural gas carriers, which are high value-added vessels such as offshore plants. However, HIL tests conducted by research institutes, including domestic shipyards, can be protracted. To address the said issue, this study proposes a field programmable gate array (FPGA) based PMS-HIL simulator that comprises a power supply, consumer, control console, and main switchboard. The proposed HIL simulation platform incorporated actual equipment data while conducting load sharing PMS tests. The proposed system was verified through symmetric, asymmetric, and fixed load sharing tests. The proposed system can thus potentially replace the standard factory acceptance tests. Furthermore, the proposed simulator can be helpful in developing additional systems for vessel automation and autonomous operation, including the development of energy management systems.

Development of Electron-Beam Lithography Process Simulation Tool of the T-shaped Gate Formation for the Manufacturing and Development of the Millimeter-wave HEMT Devices (밀리미터파용 HEMT 소자 개발 및 제작을 위한 T-게이트 형성 전자빔 리소그래피 공정 모의 실험기 개발)

  • 손명식;김성찬;신동훈;이진구;황호정
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.5
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    • pp.23-36
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    • 2004
  • A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process has been developed for sub-0.l${\mu}{\textrm}{m}$ T-shaped gate formation in the HEMT devices for millimeter-wave frequencies. For the exposure process by electron to we newly and efficiently modeled the inner-shell electron scattering and its discrete energy loss with an incident electron for multi-layer resists and heterogeneous multi-layer targets in the MC simulation. In order to form the T-gate shape in resist layers, we usually use the different developer for each resist layer to obtain good reproducibility in the fabrication of HEMT devices. To model accurately the real fabrication process of electron beam lithography, we have applied the different developers in trilayer resist system By using this model we have simulated and analyzed 0.l${\mu}{\textrm}{m}$ T-gate fabrication process in the HEMT devices, and showed our simulation results with the SEM observations of the T-shaped gate process.

Performance Analysis of Tri-gate FinFET for Different Fin Shape and Source/Drain Structures (Tri-gate FinFET의 fin 및 소스/드레인 구조 변화에 따른 소자 성능 분석)

  • Choe, SeongSik;Kwon, Kee-Won;Kim, SoYoung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.7
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    • pp.71-81
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    • 2014
  • In this paper, the performance variations of tri-gate FinFET are analyzed for different fin shapes and source/drain epitaxy types using a 3D device simulator(Sentaurus). If the fin shape changes from a rectangular shape to a triangular shape, the threshold voltage increases due to a non-uniform potential distribution, the off-current decreases by 72.23%, and the gate capacitance decreases by 16.01%. In order to analyze the device performance change from the structural change of the source/drain epitaxy, we compared the grown on the fin (grown-on-fin) structure and grown after the fin etch (etched-fin) structure. 3-stage ring oscillator was simulated using Sentaurus mixed-mode, and the energy-delay products are derived for the different fin and source/drain shapes. The FinFET device with triangular-shaped fin with etched-fin source/drain type shows the minimum the ring oscillator delay and energy-delay product.

Analysis of the Contact Pressure Distribution and Kinetics of Knee Implant Using the Simulator (Simulator를 이용한 인공무릎관절 접촉면의 압력분포 및 운동성 분석)

  • 이문규;김종민;김동민;최귀원
    • Journal of Biomedical Engineering Research
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    • v.24 no.4
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    • pp.363-367
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    • 2003
  • Contact area and pressure are important factors which directly influence a life of knee implants. Since implant's mechanical functions should be experimentally evaluated for clinical use, many studies using a knee simulator and a pressure sensor system have been conducted. However it has not been reported that the contact pressure's distribution of a knee implant motion was estimated in real-time during a gate cycle. Therefore. the objective of this study was to analyze the contact pressure distribution for the motion of a joint using the knee simulator and I-scan sensor system. For this purpose, we developed a force-controlled dynamic knee simulator to evaluate the mechanical performance of artificial knee joint. This simulator includes a function of a soft tissue and has a 4-degree-of-freedom to represent an axial compressive load and a flexion angle. As axial compressive force and a flexion angle of the femoral component can be controlled by PC program. The pressure is also measured from I-scan system and simulator to visualize the pressure distribution on the joint contact surfaces under loading condition during walking cycle. The compressive loading curve was the major cause for the contact pressure distribution and its center move in a cycle as to a flexion angie. In conclusion, this system can be used to evaluate to the geometric interaction of femoral and tibial design due to a measured mechanical function such as a contact pressure, contact area and a motion of a loading center.

A Study on Cycle Based Simulator of a 32 bit floating point DSP (32비트 부동소수점 DSP의 Cycle Based Simulator에 관한 연구)

  • 우종식;양해용;안철홍;박주성
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.35C no.11
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    • pp.31-38
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    • 1998
  • This paper deals with CBS(Cycle Base Simulator) design of a 32 bit floating point DSP(Digital Signal Processor). The CBS has been developed for TMS320C30 compatible DSP and will be used to confirm the architecture, functions of sub-blocks, and control signals of the chip before the detailed logic design starts with VHDL. The outputs from CBS are used as important references at gate level design step because they give us control signals, output values of important blocks, values from internal buses and registers at each pipeline step, which are not available from the commercial simulator of DSP. In addition to core functions, it has various interfaces for efficient execution and convenient result display, CBS is verified through comparison with results from the commercial simulator for many application algorithms and its simulation speed is as fast as several tenth of that of logic simulation with VHDL. CBS in this work is for a specific DSP, but the concept may be applicable to other VLSI design.

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A Study on the Validity of C-V Method for Extracting the Effective Channel Length of MOSFET) (MOSFET의 Effective Channel Length를 추출하기 위한 C-V 방법의 타당성 연구)

  • 이성원;이승준;신형순
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.10
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    • pp.1-8
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    • 2002
  • C- V method is a means to determine the effective channel length for miniaturized MOSFET's. This method achieves L$_{eff}$ by extracting a unique channel length independent extrinsic overlap length($\Delta$L) at a critical gate bias point. In this paper, we conducted an experiment on two different C-V methods. L$_{eff}$ extracted from experiment is compared with L$_{eff}$ simulated from a two-dimensional (2-D) device simulator, and the accuracy of C-V method for L$_{eff}$ extraction is analyzed.

A New SOl LIGBT Structure with Improved Latch-Up Performance

  • Sung, Woong-Je;Lee, Yong-11;Park, Woo-Beom;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.283-285
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    • 2001
  • In this paper, a new lateral insulated gate bipolar transistor (LIGBT) is proposed to improve the latch-up performance without current path underneath the n+ cathode region. The improvement of latch-up performance is verified using the two-dimensional simulator MEDICI and the simulation results on the latch-up current density are 3.12${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the proposed LIGBT and 0.94${\times}$10$\^$-4/ A/$\mu\textrm{m}$ for the conventional LIGBT. The proposed SOI LIGBT exhibits 3 times larger latch-up capability than the conventional SOI LIGBT.

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Numerical Analysis on the Electrical Characteristics of FS TIGBT

  • Lee, Jong-Seok;Kang, Ey-Goo;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.63-64
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    • 2006
  • Here we present detailed simulation results of trench field stop IGBTs. Besides the reduced on-state voltage drop there is also an Increase of forward blocking voltage. A trench gate IGBT has low on-state voltage drop mainly due to the removal of the JFET region and a field stop IGBT has high forward blocking voltages due to the trapezoidal field distribution under blocking condition. We have simulated the static characteristics of TIGBT with field stop technology by 2D simulator(MEDICI). The simulated result of forward blocking voltage and on-state voltage drop is about 1,408V and 1.3V respectively at $110{\mu}m$ N-drift thickness.

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