• 한국항해항만학회:학술대회논문집
• /
• 한국항해항만학회 2006년도 추계학술대회 논문집(제1권)
• /
• pp.325-330
• /
• 2006

컨테이너 터미널은 육상수송과 해상 수송의 연결기능을 수행하는 복합 운송시스템이다. 이 시스템은 내부적으로 본선 작업 시스템, 구내 이적 시스템, 장치/보관 시스템, 게이트 작업 시스템, 정보 관리 시스템등의 운영시스템을 가진다. 본 논문에서는 터미널의 배치평가와 컨테이너 장비의 찰용도 평가를 주요 목적으로 하여 장치장과 선석의 배치 대안에 대한 평가, 취급 장비의 개별적인 운영 효율성을 평가는 시뮬레이터의 개발이 목적이다. 시뮬레이션 모형의 개발은 설게 및 모델링 단계에서 재사용이 높고 모듈화하여 이식이 용이한 객체 지향 기법을 이용하였다.

• ETRI Journal
• /
• 제27권5호
• /
• pp.628-634
• /
• 2005

From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제52권6호
• /
• pp.257-260
• /
• 2003

We have proposed the junction termination structure of IGBT (Insulated Gate Bipolar Transistor) by employing trench and FLR (Field Limiting Ring), which decrease the junction termination area at the same breakdown voltage. Our proposed junction termination structure, trench FLR is verified by numerical simulator MEDICI. In 600V rated device, the junction termination area is decreased 20% compared with that of the conventional FLR structure. The breakdown voltage of trench FLR with 4 trenches is 768 V, 99 % of ideal parallel-plane junction(1-D) $BV_ceo$.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
• /
• pp.789-791
• /
• 1998

Numerical simulation has been performed on a microtip field emitter structure produced by employing a CMP technology. The field distributions are estimated by using a Maxwell 2D vector simulator and the electron trajectories are obtained by solving the equation of ballistic motion of emitted electrons. The beam width observed at the phosphor has been characterized as a function of the applied voltages and the gate-to-tip distance. It has also been investigated how the electron trajectory is changed by adopting the anode switching as well as the focus electrode.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
• /
• pp.1467-1470
• /
• 1987

This paper proposes a functional simulation algorithm which decrease the internal memory space and run time in simulation of VLSI. Flip-flop, register, ram, rom, ic and fun are described as functional elements in the simulator. Especially icf is made as new functional element by combining the gate and the functional element, therefore icf is used efficiently in simulation of VLSI. The proposed algorithm is implemented on PC-AT(MS-DOS) in by Prolog-1.

• 한국농공학회:학술대회논문집
• /
• 한국농공학회 2003년도 학술발표논문집
• /
• pp.539-542
• /
• 2003

In South Korea, flooding is controlled with large or small reservoirs scattered spatially over the territory. Because recent unexpected hard-rain events requires more flood control capacities, the pre-release system is considered with the most economical alternative. In this case time and volume of discharge should be determined by the simulation. But, existing pre-release simulation system has the problem of specificity. Therefore, GASS is considered to estimate the pre-release time and volume with different configurations of pre-release system. This paper shows that pre-release simulation system could be constructed with arranging GASAtmosphere, GASWatershed, Reservoir, Gate components using GASS. It is also shows that GASS could be used as a foundation for constructing pre-release simulation system that is easy to use and is flexible to reflect the changing configurations of reservoir systems.

• 한국전기전자재료학회논문지
• /
• 제21권8호
• /
• pp.711-714
• /
• 2008

Metal-oxide-semiconductor (MOS) capacitors were fabricated to investigate the plasma damage caused by reactive ion etching (RIE) on (100) oriented silicon-on-insulator (SOI) substrates. The thickness of the top-gate oxide, SOI, and buried oxide layers were 10 nm, 50 nm, and 100 nm, respectively. The MOS/SOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching. The measured C-V curves were compared to the numerical results from corresponding 2-dimensional (2-D) structures by using a Silvaco Atlas simulator.

• 전자공학회논문지A
• /
• 제33A권6호
• /
• pp.220-229
• /
• 1996

We presetn sytem-level simulation methodology as well as environment setup established for CDMA digtial cellular mobile station in an effort to verify CDMA modem ASIC design. To make the system-level simulation feasible, behavioral modeling of a microcontroller was first carried out with VHDL. In addition, models written in C language were also developed to provide ASIC with realistic input data. Finally, the netlist of CDMA modem ASIC was loaded on the a hardware accelerator, which was interfaced with VHDL simulator, and ismulation was performed by excuting the actual CDMA call processing software. Simulation resutls thus obtained were confirmed by comparing them with the emulation resutls from the actual system constructed on hardware modeler. these methods were proved to be effective in both discovering in advance malfunctions when embedded in the system or design errors of ASIC and reducing simulation time by a factor of as much as 20 in case of simulation at gate-level.

• 제어로봇시스템학회논문지
• /
• 제8권1호
• /
• pp.54-59
• /
• 2002

In the three-axis control of satellites by using on-board actuators, gyros are usually used to measure the attitude angles and angular rates. The gyros are operated by electronic parts and mechanical actuators. The digital components of the electronic parts consist of largely FPGA (Field Programmable Gate Array) as one of the methods for VLSI(Very Large Scale Integrated) circuit design, while the mechanical parts provide output signal directly by mechanical actuation of a spinning rotor. In this research, a mixed mode of gyro is implemented in FGA. In addition to the hardware implementation, the simulation study was conducted by using the SABER for the mixed mode simulator. Results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are also presented to validate the FPGA implementation.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
• /
• pp.30-30
• /
• 2000

In the three axis control of satellite by using reaction wheel and gyro, a Gyro carries out measuring of the attitude angie and the attitude angular velocity. The Gyro is operated by the electronic part and the mechanic actuator. The digital part of the electronic part is consisted of the FPGA (Field Programmable Gate Array), which is one of the methods for designing VLSI (Very Large Scale Integrated Circuit), and the mechanic actuator processes the input/output data by the dynamic model. In the research of the mixed mode of Gyro, the simulation is accomplished by SABER of the mixed mode simulator and the results for the practical implementation of the satellite ACS (Attitude Control System) interfaced with the data processing are proposed.