• Title/Summary/Keyword: GATE simulation

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Study of Characteristics of Dual Channel Trench IGBT (Dual Channel을 가진 Trench Insulated Gate Biploar Transistor(IGBT)특성 연구)

  • Moon, Jin-Woo;Chung, Sang-Koo
    • Proceedings of the KIEE Conference
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    • 2001.07c
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    • pp.1469-1471
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    • 2001
  • A Dual Channel Trench IGBT (Insulated Gate Bipolar Transistor) is proposed to improve the latch-up characteristics. Simulation results by MEDICI have shown that the latching current density of proposed device was found to be 2850 A/$cm^2$ while that of conventional device was 1610 A/$cm^2$. The latching current desity of the proposed strucutre was 77.02% higher than that of conventional structre.

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Implementation of a Learning Controller for Repetitive Gate Control of Biped Walking Robot (이족 보행 로봇의 반복 걸음새 제어를 위한 학습제어기의 구현)

  • Lim, Dong-Cheol;Oh, Sung-Nam;Kuc, Tae-Yong
    • Proceedings of the KIEE Conference
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    • 2005.10b
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    • pp.594-596
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    • 2005
  • This paper present a learning controller for repetitive gate control of biped robot. The learning control scheme consists of a feedforward learning rule and linear feedback control input for stabilization of learning system. The feasibility of learning control to biped robotic motion is shown via dynamic simulation and experimental results with 24 DOF biped robot.

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Development of a Monte Carlo Simulator for Electron Beam Lithography in Multi-Layer Resists and Multi-Layer Substrates (다층 리지스트 다층 기판 구조에서의 전자빔 리소그래피 공정을 위한 몬테카를로 시뮬레이터의 개발)

  • 손명식;이진구;황호정
    • Proceedings of the IEEK Conference
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    • 2002.06b
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    • pp.53-56
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    • 2002
  • We have developed a Monte Carlo (MC) simulator for electron beam lithography in multi-layer resists and multi-layer substrates in order to fabricate and develop high-speed PHEMT devices for millimeter- wave applications. For the deposited energy calculation to multi-layer resists by electron beam in MC simulation, we modeled newly for multi-layer resists and heterogeneous multi-layer substrates. Using this model, we simulated T-gate or r-gate fabrication process in PHEMT device and showed our results with SEM observations.

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A new drian-current model kof GaAs MESFET (GaAs MESFET의 새로운 드레인 전류 모델)

  • 조영송;신철재
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.8
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    • pp.64-70
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    • 1995
  • A new DC drain-current model of GaAs MESFET with improved accuracy is proposed in this paper. The proposed model includes the decrease of current slope according to gate voltages. It is possible to represent a transconductance compression using the proposed model. It shows improved transconductance and output resistance in accuracy from the forward biased gate region to near the cutoff region. The wquaer error of saturation current is decreased by 46% compared with Statz model. The proposed model can be useful for the simulation of large-signal operation and harmonic distortion.

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A Study on Shortcircuit Fault Protection Method Using Rogowski Coil (Rogowski 코일을 이용한 과전류 폴트 차단 기법에 관한 연구)

  • Yoon, Hanjong;Cho, Younghoon
    • Proceedings of the KIPE Conference
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    • 2018.07a
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    • pp.108-110
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    • 2018
  • This paper proposes shortcircuit fault protection method in a synchronous buck converter using the PCB pattern Rogowski coil. The PCB pattern Rogowski coils are embedded in the gate driver to measure the device currents of the top and bottom side. When shortcircuit occurs in the system, the gate signal is blocked by the proposed fault protection method using the device current. The simulation and experimental results show that the proposed fault protection method is verified in the shortcircuit system.

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Two-dimensional numerical simulation study on the nanowire-based logic circuits (나노선 기반 논리 회로의 이차원 시뮬레이션 연구)

  • Choi, Chang-Yong;Cho, Won-Ju;Chung, Hong-Bay;Koo, Sang-Mo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.82-82
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    • 2008
  • One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

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A Study on the Dual Emitter Structure 4H-SiC-based LIGBT for Improving Current Driving Capability (전류 구동 능력 향상을 위한 듀얼 이미터 구조의 4H-SiC 기반 LIGBT에 관한 연구)

  • Woo, Je-Wook;Lee, Byung-Seok;Kwon, Sang-Wook;Gong, Jun-Ho;Koo, Yong-Seo
    • Journal of IKEEE
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    • v.25 no.2
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    • pp.371-375
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    • 2021
  • In this paper, a SiC-based LIGBT structure that can be used at high voltage and high temperature is presented. In order to improve the low current characteristic, a dual-emitter symmetrical around the gate is inserted. In order to verify the characteristics of the proposed device, simulation and design were conducted using Sentaurus TCAD simulation, and a comparative study was conducted with a general LIGBT. In addition, splitting was performed by designating a variable for the length of the N-drift region in order to verify the electrical characteristics of the minority carriers. As a result of the simulation it was confirmed that the proposed dual-emitter structure flows a higher current at the same voltage than the conventional LIGBT.

Similarity analysis of pixelated CdTe semiconductor gamma camera image using a quadrant bar phantom for nuclear medicine: Monte Carlo simulation study

  • Park, Chan Rok;Kang, Seong-Hyeon;Lee, Youngjin
    • Nuclear Engineering and Technology
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    • v.53 no.6
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    • pp.1947-1954
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    • 2021
  • In the nuclear medicine imaging, quality control (QC) process using quadrant bar phantom is fundamental aspect of evaluating the spatial resolution. In addition, QC process of gamma camera is performed by daily or weekly. Recently, Monte Carlo simulation using the Geant4 application for tomographic emission (GATE) is widely applied in the pre-clinical nuclear medicine field for modeling gamma cameras with pixelated cadmium telluride (CdTe) semiconductor detector. In this study, we modeled a pixelated CdTe semiconductor detector and quadrant bar phantom (0.5, 1.0, 1.5, and 2.0 mm bar thicknesses) using the GATE tool. Similarity analysis based on correlation coefficients and peak signal-to-noise ratios was performed to compare image qualities for various source to collimator distances (0, 2, 4, 6, and 8 cm) and collimator lengths (0.2, 0.4, 0.6, 0.8, and 1.0 cm). To this end, we selected reference images based on collimator length and source to collimator distance settings. The results demonstrate that as the collimator length increases and the source to collimator distance decreases, the similarity to reference images improves. Therefore, our simulation results represent valuable information for the modeling of CdTe-based semiconductor gamma imaging systems and QC phantoms in the field of nuclear medicine.

Simulation and assessment of 99mTc absorbed dose into internal organs from cardiac perfusion scan

  • Saghar Salari;Abdollah Khorshidi;Jamshid Soltani-Nabipour
    • Nuclear Engineering and Technology
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    • v.55 no.1
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    • pp.248-253
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    • 2023
  • Directly, it is not possible to measure the absorbed dose of radiopharmaceuticals in the organs of the human body. Therefore, simulation methods are utilized to estimate the dose in distinct organs. In this study, individual organs were separately considered as the source organ or target organ to calculate the mean absorption dose, which SAF and S factors were then calculated according to the target uptake via MIRD method. Here, 99mTc activity distribution within the target was analyzed using the definition and simulation of ideal organs by summing the fraction of cumulative activities of the heart as source organ. Thus, GATE code was utilized to simulate the Zubal humanoid phantom. To validate the outcomes in comparison to the similar results reported, the accumulation of activity in the main organs of the body was calculated at the moment of injection and cardiac rest condition after 60 min of injection. The results showed the highest dose absorbed into pancreas was about 21%, then gallbladder 18%, kidney 16%, spleen 15%, heart 8%, liver 8%, thyroid 7%, lungs 5% and brain 2%, respectively, after 1 h of injection. This distinct simulation model may also be used for different periods after injection and modifying the prescribed dose.

Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy (예측정확도 향상 전략을 통한 예측기반 병렬 게이트수준 타이밍 시뮬레이션의 성능 개선)

  • Yang, Seiyang
    • KIPS Transactions on Computer and Communication Systems
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    • v.5 no.12
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    • pp.439-446
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    • 2016
  • In this paper, an efficient prediction accuracy enhancement strategy is proposed for improving the performance of the prediction-based parallel event-driven gate-level timing simulation. The proposed new strategy adopts the static double prediction and the dynamic prediction for input and output values of local simulations. The double prediction utilizes another static prediction data for the secondary prediction once the first prediction fails, and the dynamic prediction tries to use the on-going simulation result accumulated dynamically during the actual parallel simulation execution as prediction data. Therefore, the communication overhead and synchronization overhead, which are the main bottleneck of parallel simulation, are maximally reduced. Throughout the proposed two prediction enhancement techniques, we have observed about 5x simulation performance improvement over the commercial parallel multi-core simulation for six test designs.