• Korean Journal of Materials Research
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• v.3 no.2
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• pp.158-165
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• 1993

Abstract To investigate the effect of underlying Si on the thermal stability of the TiS$i_2$ film, TiS$i_2$ films obtained by the solid-state reaction of the Ti film on as-deposited or on heat-treated poly-silicon and amorphous-silicon were annealed at 90$0^{\circ}C$ for various times. The poly-Si film was evaluated by XRD, SEM and TEM. The thermal stability of the TiS$i_2$ film was evaluated by measuring the sheet resistance and microstructural evolution during furnace annealing. Agglomeration of the TiSi, film occurred more on amorphous-Si than on poly-Si. The thermal stability of the TiS$i_2$ film was improved by annealing poly-Si. The Si layer crystallized from amorphous-Si has an equiaxed structure with the (111) preferred orientation whereas for as-deposited poly-Si has a columnar structure with the (110) orientation. Better thermal stability of the TiS$i_2$ film can be obtained by the higher surface energy of underlying poly-Si.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.97-97
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• 2013

Recently, Cu2ZnSn(S,Se)4 (CZTSS), which is one of the In- and Ga- free absorber materials, has been attracted considerable attention as a new candidate for use as an absorber material in thin film solar cells. The CZTSS-based absorber material has outstanding characteristics such as band gap energy of 1.0 eV to 1.5 eV, high absorption coefficient on the order of 104 cm-1, and high theoretical conversion efficiency of 32.2% in thin film solar cells. Despite these promising characteristics, research into CZTSS based thin film solar cells is still incomprehensive and related reports are quite few compared to those for CIGS thin film solar cells, which show high efficiency of over 20%. I will briefly overview the recent technological development of CZTSS thin film solar cells and then introduce our research results mainly related to sputter based process. CZTSS thin film solar cells are prepared by sulfurization of stacked both metallic and sulfide precursors. Sulfurization process was performed in both furnace annealing system and rapid thermal processing system using S powder as well as 5% diluted H2S gas source at various annealing temperatures ranging from $520^{\circ}C$ to $580^{\circ}C$. Structural, optical, microstructural, and electrical properties of absorber layers were characterized using XRD, SEM, TEM, UV-Vis spectroscopy, Hall-measurement, TRPL, etc. The effects of processing parameters, such as composition ratio, sulfurization pressure, and sulfurization temperature on the properties of CZTSS absorber layers will be discussed in detail. CZTSS thin film solar cell fabricated using metallic precursors shows maximum cell efficiency of 6.9% with Jsc of 25.2 mA/cm2, Voc of 469 mV, and fill factor of 59.1% and CZTS thin film solar cell using sulfide precursors shows that of 4.5% with Jsc of 19.8 mA/cm2, Voc of 492 mV, and fill factor of 46.2%. In addition, other research activities in our lab related to the formation of CZTS absorber layers using solution based processes such as electro-deposition, chemical solution deposition, nano-particle formation will be introduced briefly.

• Journal of the Korean Magnetics Society
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• v.6 no.3
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• pp.165-169
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• 1996

The relationship between grain size and number of magnetic domain walls for tertiary recrystallized ultra thin 3 % Si-Fe strips was investigated. It was found that the strips with different grain size can be produced by controlling the inserting speed of sample in annealing furnace. Though grain size of the stirip became smaller than 1mm, $B_{8}$ of high value above 1.95T was obtained. But $H_{c}$ increased with decaying the grain size. The magnetic domains and losses of the ultra thin grain oriented silicon steel with smaller grian size were observed. The eddy current losses of the strips were decreased with decreasing the grain size in high frequency range because strips with smaller grain have narrower magnetic domain wall spacings. But Hysteresis losses of the strips with smaller grain have high value in low frequency range. Therefore the iron loss of ultra thin grain oriented silicon steel could be controlled by the grain size. It was clarified that the minumum tatal loses depended on the exciting frequency and grain size.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.371-374
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• 2004

In this paper, Ni Germane-silicide formed on undoped $Si_{0.8}Ge_{0.2}$ as well as source/drain dopants doped $Si_{0.8}Ge_{0.2}$ was characterized by the four-point probe for sheet resistance. x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and field emission scanning electron microscope (FESEM). Low resistive NiSiGe is formed by one step RTP (Rapid thermal processing) with temperature range at $500{\~}700^{\circ}C$. To enhance the thermal stability of Ni Germane-silicide, Ni/Co/TiN structure with different Co concentration were studied in this work. Low sheet resistance was obtained by Ni/Co/TiN structure with high Co concentration using 2-step RTP and it almost keeps the same low sheet resistance even after furnace annealing at $650^{\circ}C$ for 30 min.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.310-310
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• 2016

최근 NAND flash memory는 높은 집적성과 데이터의 비휘발성, 낮은 소비전력, 간단한 입, 출력 등의 장점들로 인해 핸드폰, MP3, USB 등의 휴대용 저장 장치 및 노트북 시장에서 많이 이용되어 왔다. 특히, 최근에는 smart watch, wearable device등과 같은 차세대 디스플레이 소자에 대한 관심이 증가함에 따라 유연하고 투명한 메모리 소자에 대한 연구가 다양하게 진행되고 있다. 대표적인 플래시 메모리 소자의 구조로 charge trapping type flash memory (CTF)가 있다. CTF 메모리 소자는 trap layer의 trap site를 이용하여 메모리 동작을 하는 소자이다. 하지만 작은 window의 크기, trap site의 열화로 인해 메모리 특성이 나빠지는 문제점 등이 있다. 따라서 최근, trap layer에 다양한 물질을 적용하여 CTF 소자의 문제점을 해결하고자 하는 연구들이 진행되고 있다. 특히, 산화물 반도체인 zinc oxide (ZnO)를 trap layer로 하는 CTF 메모리 소자가 최근 몇몇 보고 되었다. 산화물 반도체인 ZnO는 n-type 반도체이며, shallow와 deep trap site를 동시에 가지고 있는 독특한 물질이다. 이 특성으로 인해 메모리 소자의 programming 시에는 deep trap site에 charging이 일어나고, erasing 시에는 shallow trap site에 캐리어들이 쉽게 공급되면서 deep trap site에 갇혀있던 charge가 쉽게 de-trapped 된다는 장점을 가지고 있다. 따라서, 본 실험에서는 산화물 반도체인 ZnO를 trap layer로 하는 CTF 소자의 메모리 특성을 확인하기 위해 간단한 구조인 metal-oxide capacitor (MOSCAP)구조로 제작하여 메모리 특성을 평가하였다. 먼저, RCA cleaning 처리된 n-Si bulk 기판 위에 tunnel layer인 SiO2 5 nm를 rf sputter로 증착한 후 furnace 장비를 이용하여 forming gas annealing을 $450^{\circ}C$에서 실시하였다. 그 후 ZnO를 20 nm, SiO2를 30 nm rf sputter로 증착한 후, 상부전극을 E-beam evaporator 장비를 사용하여 Al 150 nm를 증착하였다. 제작된 소자의 신뢰성 및 내구성 평가를 위해 상온에서 retention과 endurance 측정을 진행하였다. 상온에서의 endurance 측정결과 1000 cycles에서 약 19.08%의 charge loss를 보였으며, Retention 측정결과, 10년 후 약 33.57%의 charge loss를 보여 좋은 메모리 특성을 가지는 것을 확인하였다. 본 실험 결과를 바탕으로, 차세대 메모리 시장에서 trap layer 물질로 산화물 반도체를 사용하는 CTF의 연구 및 계발, 활용가치가 높을 것으로 기대된다.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.206.1-206.1
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• 2015

최근에 금속산화물을 증착하는 방법으로 용액공정이 주목 받고 있다. 용액 공정은 대기압에서 매우 간단한 방법으로 복잡한 공정과정을 요구하지 않기 때문에 박막을 경제적으로 간단하게 형성할 수 있다. 하지만 용액공정을 통해 형성한 박막에는 소자의 특성을 열화 시키는 solvent와 탄소계열의 불순물을 많이 포함하고 있어 고온의 열처리가 필수적이다. 박막의 품질을 향상시키기 위해서 다양한 열처리 방법들이 이용되고 있으며, 일반적인 열처리 방법으로는 furnace를 이용한 conventional thermal annealing (CTA)이 많이 이용되고 있다. 하지만, 최근에는 microwave를 이용한 공정이 주목 받고 있다. Microwave energy는 CTA보다 효과적으로 비교적 낮은 온도에서 높은 열처리 효과를 나타낸다. 본 실험은 n-type Silicon 기판에 solution-ZrO2 산화막을 형성 후, oven baking을 한 뒤, CTA와 microwave를 이용하여 solvent와 불순물을 제거 하였다. 전기적 특성을 확인하기 위해 solution ZrO2 산화막 위에 E-beam evaporator를 이용해 Ti 금속 전극을 증착하여 Metal-Oxide-Semiconductor (MOS) capacitor를 제작하였다. 다음으로, PRECISION SEMICONDUCTOR PARAMETER ANALYZER (4156B)를 이용하여, capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 비교하였다. 다음으로, CTA를 통하여 제작한 소자와 전기적 특성을 비교하였다. 그 결과, Microwave irradiation으로 열처리한 MOS capacitor 소자에서 capacitance 값과 flat band voltage, hysteresis 등이 개선되는 효과를 확인하였다. Microwave irradiation 열처리는 100oC 미만의 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 ZrO2 용액의 불순물과 solvent를 낮은 온도에서 제거하여 고품질 박막 형성에 매우 효과적이라는 것을 나타낸다. 따라서, microwave irradiation 열처리 방법은 비정질 산화막이 포함되는 박막 transistor 소자 제작에 대하여 결정적인 열처리 방법이 될 것으로 기대한다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.3
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• pp.141-145
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• 2018

Ni-InGaAs shows promise as a self-aligned S/D (source/drain) alloy for n-InGaAs MOSFETs (metal-oxide-semiconductor field-effect transistors). However, limited thermal stability and instability of the microstructural morphology of Ni-InGaAs could limit the device performance. The in situ deposition of a Pd interlayer beneath the Ni layer was proposed as a strategy to improve the thermal stability of Ni-InGaAs. The Ni-InGaAs alloy layer prepared with the Pd interlayer showed better surface roughness and thermal stability after furnace annealing at $570^{\circ}C$ for 30 min, while the Ni-InGaAs without the Pd interlayer showed degradation above $500^{\circ}C$. The Pd/Ni/TiN structure offers a promising route to thermally immune Ni-InGaAs with applications in future n-InGaAs MOSFET technologies.

• Journal of the Korean Society for Nondestructive Testing
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• v.34 no.3
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• pp.241-247
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• 2014

This study presents the ultrasonic nonlinearity of AISI316 austenitic stainless steels subjected to longterm isothermal aging. These steels are attractive materials for use in industrial mechanical structures because of their strength at high-temperatures and their chemical stability. The test materials were subjected to accelerated heat-treatment in an electrical furnace for a predetermined aging duration. The variations in the ultrasonic nonlinearity and microstructural damage were carefully evaluated through observation of the microstructure. The ultrasonic nonlinearity stiffly dropped after aging for up to 1000 h and, then, monotonously decreased. The polygonal shape of the initial grain structures changed to circular, especially as the annealing twins in the grains dissolved and disappeared. The delta ferrite on the grain boundaries could not be observed at 1000 h of aging, and these continuously transformed into their sigma phases. Consequently, in the intial aging period, the rapid decrease in the ultrasonic nonlinearity was caused by voids, dislocations, and twin annihilation. The continuous monotonic decrease in the ultrasonic nonlinearity after the first drop resulted from the generation of $Cr_{23}C_6$ precipitates and ${\sigma}$ phases.

• Journal of Sensor Science and Technology
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• v.10 no.3
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• pp.173-179
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• 2001

The currently used semiconductor pressure sensors are piezoresistive and capacitive type. Especially, semiconductor micro pressure sensors have a great deal of attention because of their small size. However, its fabrication processes are difficult, so that its yield is poor. For the purpose of resolving the drawbacks of the existing silicon pressure sensors, we demonstrate a new type of pressure sensor using PSFET(pressure sensitive field effect transistor) and investigate its operational characteristics. We used PZT(Pb(Zr,Ti)$O_3$) as a pressure sensing material. PZT thin films were deposited on a gate oxide of MOSFET by an rf-magnetron sputtering method. To abtain the stable phase, perovskite structure, furnace annealing technique have been employed in PbO ambient. The sensitivity of the PSFET was 0.38 mV/mmHg.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.129-130
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• 2006

A stoichiometric mixture of evaporating materials for $CdIn_2S_4$ single crystal thin films was prepared from horizontal furnace. To obtain the single crystal thin films, $CdIn_2S_4$ mixed crystal was deposited on thoroughly etched semi-insulating GaAs(100) substrate by hot wall epitaxy(HWE) system. The source and substrate temperatures were $630^{\circ}C$ and $420^{\circ}C$, respectively. After the as-grown $CdIn_2S_4$ single crystal thin films was annealed in Cd-, S-, and In-atmospheres, the origin of point defects of $CdIn_2S_4$ single crystal thin films has been investigated by the photoluminescence(PL) at 10 K. The native defects of $V_{cd}$, $V_s$, $Cd_{int}$, and $S_{int}$, obtained by PL measurements were classified as a donors or acceptors type. And we concluded that the heat-treatment m the S-atmosphere converted $CdIn_2S_4$ single crystal thin films to an optical p-type. Also. we confirmed that In in $CdIn_2S_4$/GaAs did not form the native defects because In in $CdIn_2S_4$ single crystal thin films existed in the form of stable bonds.