• Journal of the Korean institute of surface engineering
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• v.38 no.1
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• pp.7-13
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• 2005

Bismuth thin films were prepared on glass substrate with RF magnetron sputtering and effects of substrate temperature on surface morphology and their electrical transport properties were investigated. Grain growth of bismuth after nucleation and the onset of coalescense of grains at 393 K were observed with field emission secondary electron microscopy. Continuous thin films could not be obtained above 473 K because of grain segregation and island formation. Hall effect measurements showed that substrate heating yields the decrease of carrier density and the increase of mobility. Resistivity of bismuth film has its minimum (about 0.7 x 10/sup -3/ Ωcm) in range of 403～433 K. Annealing of bismuth films deposited at room temperature was carried out in a radiation furnace with flowing hydrogen gas. The change of resistivity was not significant due to cancellation of the decrease of carrier density and the increase of mobility. The abrupt change of electrical properties of film annealed above 523 K was found to be caused by partial oxidation of bismuth layer in x-ray diffraction analysis.

• Journal of Sensor Science and Technology
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• v.13 no.4
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• pp.303-308
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• 2004

This paper descibes on the characteristics of Ta-N(tantalum nitride) ceramic thin-film strain gauges which were deposited on Si substrates by DC reactive magnetron sputtering in an argon-nitrogen atmosphere (Ar-$(4{\sim}16%)N_{2}$) for high-temperature applications. These films were annealed in $2{\times}10^{-6}$ Torr vacuum furnace at the range of $500{\sim}1000^{\circ}C$. Optimum deposition atmosphere and annealing temperature were determined at $900^{\circ}C$ for 1 hr. in 8% $N_{2}$ gas flow ratio. Under optimum formation conditions, the Ta-N thin-film for strain gauges was obtained a high-resistivity of $768.93{\mu}{\Omega}{\cdot}cm$, a low temperature coefficient of resistance (TCR) of -84 ppm/$^{\circ}C$ and a good longitudinal gauge factor (GF) of 4.12.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.1017-1020
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• 2002

The pure Ti is taken annealing process for one hour at 90$0^{\circ}C$. The pure Ti is sufficient for ASTM B348 Grade2. The rolling mill roll the Ti-8Ta-3Nb(wt%) which became vacuum melting in arc furnace until the length is about 45mm and the thickness is about 6.05mm. Then it is made 6mm$\times$6mm$\times$44mm by wire cutting with EDM and it is made ∮ 6mm by rough cutting with the general purpose lathe. The machining accuracy of implant parts in the dental and medical science are decided by dimension, shpe, straightness, surface roughness. It is difficult to cut for the Ti alloy. It is caused problems of straight degree and surface roughness to the Ti alloy have many cases which length is smaller than diameter in cutting. Total 24 specimens different kind of 4 alloies are used in experiment to gain a cutting property. According to the cutting velocity, cutting depth, cutting temperature, feed and clearance angle experiments are performed. Conclusively it is expected that cutting depth of 0.5mm, feed velocity of 0.07mm/rev and cutting velocity of 80m/min could make a suitable result.

• Korean Journal of Materials Research
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• v.15 no.5
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• pp.318-322
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• 2005

Ti-capped NiSi contacts were formed on $p^+/n$ junctions to improve the leakage problem and then Cu was deposited without removing the Ti-capping layer in an attempt to utilize as a diffusion barrier. The electrical characteristics of these $p^+/n$ diodes with Cu/Ti/NiSi electrodes were measured as a function of drive-in RTA(rapid-thermal annealing) and silicidation temperature and time. When drive-in annealed at $900^{\circ}C$, 10 sec. and silicided at $500^{\circ}C$, 100 sec., the diodes showed the most excellent I-V characteristics. Especially, the leakage current was $10^{-10}A$, much lower than reported data for diodes with NiSi contacts. However, when the $p^+/n$ diodes with Cu/Ti/NiSi contacts were furnace-annealed at $400^{\circ}C$ for 40 min., the leakage current increased by 4 orders. The FESEM and AES analysis revealed that the Ti-capping layer effectively prohibited the Cu diffusion, but was ineffective against the NiSi dissociation and consequent Ni diffusion.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.120-120
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• 2003

The metallic oxide nanomaterials including ZnO, Ga$_2$O$_3$, TiO$_2$, and SnO$_2$ have been synthesized by a number of methods including laser ablation, arc discharge, thermal annealing procedure, catalytic growth processes, and vapor transport. We have been interested in preparing the nanomaterials of Ga$_2$O$_3$, which is a wide band gap semiconductor (E$_{g}$ =4.9 eV) and used as insulating oxide layer for all gallium-based semiconductor. Ga$_2$O$_3$ is stable at high temperature and a transparent oxide, which has potential application in optoelectronic devices. The Ga$_2$O$_3$ nanoparticles and nanobelts were produced using GaN single crystals, which were grown by flux method inside SUS$^{TM}$ cell using a Na flux and exhibit plate-like morphologies with 4 ~ 5 mm in size. In these experiments, the conventional electric furnace was used. GaN single crystals were pulverized in form of powder for the growth of Ga$_2$O$_3$ nanomaterials. The structure, morphology and composition of the products were studied mainly by X-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and high-resolution transmission electron microscopy (HRTEM).).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.2
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• pp.189-194
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• 2006

Ordered nanostructure materials have received attention due to their unique physical properties and potential applications in electronics, mechanics and optical devices. To actualize most of the proposed applications, it is quite important to obtain highly ordered nanostructure arrays. The well-aligned nanostructure can be achieved by synthesizing nanostructure material in the highly ordered template. To get well-aligned pore array and reduce process time, rapid thermal anneal by an IR lamp was employed in vacuum state at $500^{\circ}C$ for 2 hour. The pore array is comparable to a template annealed in vacuum furnace at $500^{\circ}C$ for 30 hours. The well-fabricated AAO template has the mean pore diameter of 70 nm, the barrier layer thickness of 25 nm, the pore depth of $9{\mu}m$, and the pore density of higher than $1.2{\times}10^{10}cm^{-2}$.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.501-504
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• 2006

The Process technology for uniform SLS poly-Si and performance enhancement of furnace activated poly-Si TFTs are reported. By strictly optimizing SLS optics, threshold voltage variation in pixel TFTs was remarkably decreased and the non-uniformity such as SLS shot mark was removed. Optimized doping process for low sheet resistance and passivation annealing are critical for the enhancement of device performances.

• Proceedings of the KIEE Conference
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• 1989.11a
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• pp.122-126
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• 1989

A composite polycide struoture consisting of refractory metal and noble metal silicide film on top of polysilicon bas been considered as a replacement for polysilicon as a gate electrode and Interconnect line in MOSFET integrated circuits. In this paper presents divice characteristics of NOS with $TiSi_2/n^+$polyoide and $CoSi_2/n^+$polycide gate. Also, evaporated Ti,Co films on polysilicon has been annealed by RTA and furnace annealing in $N_2$ abient at temperature of $400^{\circ}C-1000^{\circ}C$. The Ti-,Co-silioide formation is characterized by 4-point probe, silicide growth rate and Its reproductivity bas been examined by SEM.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.339-343
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• 2005

Pt-$SrBi_2Nb_2O_9(SBN)-Pt-Y_2O_3-Si$ gate field effect transistors (MFMISFETs) have been fabricated and the SBN thin films are rapid thermal annealed in oxygen plasma. The grain size of the SBN becomes 4 times much larger than that of furnace annealed SBN films even at the same annealing temperature of $700^{\circ}C$, remnant polarization value of Pt-SBN-Pt is improved by 2 times. Using the rapid grain growth of SBN for the MFM-ISFET, memory window and programming characteristics of on/off states are fairly well improved.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.480.1-480.1
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• 2014

In this study, we suggest the new emitter formation applied solid phase epitaxy (SPE) growth process using rapid thermal process (RTP). Preferentially, we describe the SPE growth of intrinsic a-Si thin film through RTP heat treatment by radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD). Phase transition of intrinsic a-Si thin films were taken place under $600^{\circ}C$ for 5 min annealing condition measured by spectroscopic ellipsometer (SE) applied to effective medium approximation (EMA). We confirmed the SPE growth using high resolution transmission electron microscope (HR-TEM) analysis. Similarly, phase transition of P doped a-Si thin films were arisen $700^{\circ}C$ for 1 min, however, crystallinity is lower than intrinsic a-Si thin films. It is referable to the interference of the dopant. Based on this, we fabricated 16.7% solar cell to apply emitter layer formed SPE growth of P doped a-Si thin films using RTP. We considered that is a relative short process time compare to make the phosphorus emitter such as diffusion using furnace. Also, it is causing process simplification that can be omitted phosphorus silicate glass (PSG) removal and edge isolation process.