• Korean Journal of Crystallography
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• v.1 no.1
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• pp.29-34
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• 1990

Single crystals of the peritectic compound MgTiO3 up to 8 m diameter and 100mm long along the [1010] axis. were yon by the travelling solvent floating zone technique using a halogen lamp image furnace. The grown single crystal. which shows a solid solution range at high temperature, exsolves TiO2 component if it is annealed very slowly to room termperature. Grown boules were black but become translucent with pinkish brown color after tempering at 1100 t for 8-10 hours in oxygen atmosphere and showed distint chatoyancy along the (0001) plane. The grown crystal can be used as a new modified cat's eye gemstone. The optimum conditions were as follows ;Sintering temperature of the charge rod, 1300℃ the growth rate, 2-2.5mmh and the composition of the charge rod in molar ratio. MgO : TiO2 : 1:1.05.

• Korean Journal of Materials Research
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• v.17 no.9
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• pp.463-468
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• 2007

The interdiffusion characteristics of Cu-plug/Capping Layer/NiSi contacts were investigated. Capping layers were deposited on Ni/Si to form thermally-stable NiSi and then were utilized as diffusion barriers between Cu/NiSi contacts. Four different capping layers such as Ti, Ta, TiN, and TaN with varying thickness from 20 to 100 nm were employed. When Cu/NiSi contacts without barrier layers were furnace-annealed at $400^{\circ}C$ for 40 min., Cu diffused to the NiSi layer and formed $Cu_3Si$, and thus the NiSi layer was dissociated. But for Cu/Capping Layers/NiSi, the Cu diffusion was completely suppressed for all cases. But Ni was found to diffuse into the Cu layer to form the Cu-Ni(30at.%) solid solution, regardless of material and thickness of capping layers. The source of Ni was attributed to the unreacted Ni after the silicidation heat-treatment, and the excess Ni generated by the transformation of $Ni_2Si$ to NiSi during long furnace-annealing.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.7
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• pp.1255-1258
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• 2010

In this paper, the $CoSi_2$ thin films with thicknesses of about $5{\mu}m$ were deposited on n-type silicon (111) substrates by RF magnetron sputtering method using a $CoSi_2$ target (99.99%). The flow rate of argon of 50 sccm, substrate temperature of $100^{\circ}C$, RF power of 60 watts, deposition time of 30 minutes, and the vacuum of $1\times10^{-6}$ Torr. The annealing treatments of the $CoSi_2$ thin film were performed from 500, 700 and $900^{\circ}C$ for 1h in air ambient by an electric furnace. In order to investigate the $CoSi_2$ thin film X-ray diffraction patterns were measured using the X-ray diffractometer (XRD). The structure of the thin films were investigated by using scanning the electron microscope (SEM) were used for review. The surface morphology of the thin films was measured with a atomic force microscopy (AFM). Temperature dependence of sheet resistivity and property of Hall effect was measured in the $CoSi_2$ thin film.

• Journal of the Korean Vacuum Society
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• v.7 no.4
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• pp.368-373
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• 1998

As device dimensions approach submicrometer size in ULSI, the demand for interlayer dielectric materials with very low dielectric constant is increased to solve problems of RC delay caused by increase in parasitic resistance and capacitance in multilevel interconnectins. Fluorinated amorphous carbon in one of the promising materials in ULSI for the interlayer dielectric films with low dielectric constant. However, poor thermal stability and adhesion with Si substrates have inhibited its use. Recently, amorphous hydrogenated carbon (a-C:H) film as a buffer layer between the Si substrate and a-C:F has been introduced because it improves the adhesion with Si substrate. In this study, therfore, a-C:F/a-C:H films were deposited on p-type Si(100) by ECRCVD from $C_2F_6, CH_4$and $H_2$gas source and investigated the effect of forward power and composition on the thickness, chemical bonding state, dielectric constant, surface morphology and roughness of a-C:F films as an interlayer dielectric for ULSI. SEM, FT-IR, XPS, C-V meter and AFM were used for determination of each properties. The dielectric constant in the a-C:F/a-C:H films were found to decrease with increasing fluorine content. However, the dielectric constant increased after furnace annealing in $N_2$atomosphere at $400^{\circ}C$ for 1hour due to decreasing of flurorine content. However, the dielectric constant increased after furnace annealing in $N_2$atmosphere at $400^{\circ}C$ for 1hour due to decreasing of fluorine concentration.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.206.2-206.2
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• 2015

최근 비정질 산화물 반도체 thin film transistor(TFT)는 차세대 투명 디스플레이로 많은 관심을 받고 있으며 활발한 연구가 진행되고 있다. 산화물 반도체 TFT는 기존의 비정질 실리콘 반도체에 비하여 큰 on/off 전류비, 높은 이동도 그리고 낮은 구동전압으로 인하여 차세대 투명 디스플레이 산업에 적용 가능하다는 장점이 있다. 한편 기존의 sputter나 evaporator를 이용한 증착 방식은 우수한 막의 특성에도 불구하고 많은 시간과 제작비용이 든다는 단점을 가지고 있다. 따라서 본 연구에서는 별도의 고진공 시스템이 필요하지 않을 뿐만 아니라 대면적화에도 유리한 용액공정 방식을 이용하여 박막 트렌지스터를 제작하였으며 thermal 열처리와 microwave 열처리 방식에 따른 전기적 특성을 비교 및 분석하고 각 열처리 방식의 열처리 온도 및 조건을 최적화 하였다. 제작된 박막 트렌지스터는 p-type bulk silicon 위에 산화막이 100 nm 형성된 기판에 spin coater을 이용하여 Al-Zn-Sn-O 박막을 형성하였다. 연속해서 photolithography 공정과 BOE (30:1) 습식 식각 과정을 이용해 활성화 영역을 형성하여 소자를 제작하였다. 제작 된 소자는 Pseudo-MOS FET구조이며, 프로브 탐침을 증착 된 채널층 표면에 직접 접촉시켜 소스와 드레인 역할을 대체하여 동작시킬 수 있어 전기적 특성평가가 용이하다는 장점을 가지고 있다. 그 결과, microwave를 통해 열처리한 소자는 100oC 이하의 낮은 열처리 온도에도 불구하고 furnace를 이용하여 열처리한 소자와 비교하여 subthreshold swing(SS), Ion/off ratio, field-effectmobility 등이 개선되는 것을 확인하였다. 따라서, microwave 열처리 공정은 향후 저온 공정을 요구하는 MOSFET 제작 시의 훌륭한 대안으로 사용 될 것으로 기대된다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.124.1-124.1
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• 2011

결정질 태양전지에서 도핑(Doping)은 반도체(Semiconductor)의 PN 접합(Junction)을 형성하는 중요한 역할을 한다. 도핑은 반도체에 불순물(Dopant)을 주입하는 공정으로 고온에서 진행되며 온도는 중요한 변수(Parameter)로 작용한다. 본 연구에서는 여러 가지 도핑 방법 중 SOD(Spin-On Dopant)를 이용하여 온도에 따른 도핑 결과와 특성을 분석 하였다. P-type 웨이퍼(Wafer)에 SOD를 이용하여 불순물을 증착 후 Hot-plate에서 15분간 Baking 하였다. Baking된 웨이퍼는 노(Furnace)에 넣고 $860^{\circ}C{\sim}880^{\circ}C$까지 $10^{\circ}C$씩 가변하였다. 각각의 조건에 대해 Lifetime과 Sheet Resistance을 측정하였고, 그 결과 $880^{\circ}C$에서의 Lifetime이 $23.58{\mu}s$로 $860^{\circ}C$에 비해 235.8% 증가하여 가장 우수 하였으며, Sheet Resistance 또한 $68{\Omega}$/sq로 $860^{\circ}C$에서 가장 우수하게 측정되었다. SOD의 속도 가변에 따른 특성 변화를 보기 위해 온도는 $880^{\circ}C$에 고정한 후 속도를 3000rpm~4500rpm까지 500rpm간격으로 1시간동안 실험한 결과 rpm 속도에 따른 lifetime 변화는 거의 없었으며, Sheet Resistance는 3000rpm에서 $63{\Omega}$/sq로 가장 우수 하였다. 본 연구를 통해 온도와 Spin rpm에 따른 특성을 확인한 결과 온도가 높을 때 Sheet Resistance가 가장 안정화 되며, lifetime이 더욱 우수한 것을 확인할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.17-18
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• 2006

고상 확산 방법을 이용하여 얕은 소스/드레인 접합을 가지는 SOI (Silicon-On-Insulator) MOSFET 소자를 제작하였다. 확산원으로는 PSG(Phosphorus silicate glass) 박막과 PBF(Poly Boron Film) 박막이 각각 n, p-type 소자 형성을 위해 사용되었다. 얕은 접합 형성을 위하여 급속 열처리 방법(RTA: Rapid Thermal Annealing)을 이용하여 PSG와 PBF로부터 인과 붕소를 SOI MOSFET 소자의 소스/드레인으로 확산시켰다. 또한, 소자 특성 개선을 위한 후 속 열처리 공정으로 희석된 수소 분위기 중에서 FA(Furnace Annealing)를 실시하였다. SPD 기술을 적용하여 10 nm 이하의 매우 얕은 p-n 접합을 형성할 수 있었고, 양호한 다이오드 특성을 얻을 수 있었다. 또한, SPD 방법으로 결함이 없는 접합 형성이 가능하며, 소자 제작 공정의 최적화를 통해 차세대 CMOS 소자로 기대되는 SOI MOSFET를 성공적으로 제작할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.236-237
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• 2005

The structural properties of $(Bi,Ce)_4Ti_3O_{12}(BCT)$ thin films with post-annealing temperature were investigated. $(Bi,Ce)_4Ti_3O_{12}(BCT)$ thin films were deposited by RF sputtering method on Pt/Ti/$SiO_2$/Si substrates with optimum deposition condition. The $(Bi,Ce)_4Ti_3O_{12}(BCT)$ thin films was post-annealed at 600$^{\circ}C$, 650$^{\circ}C$, 700$^{\circ}C$, 750$^{\circ}C$, 800$^{\circ}C$ in furnace,respectively. Increasing the post-annealing temperature, the grain size, density and peak intensity of (117) and c-axis orientation were increased. The $(Bi,Ce)_4Ti_3O_{12}(BCT)$ thin films that annealed at 750$^{\circ}C$ exhibited well crystallized phase and had no vacancy and grain was uniform. but there are some secondary phases observed. At this time, the average thickness of $(Bi,Ce)_4Ti_3O_{12}(BCT)$ thin films was 2000 ${\AA}$.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.134-134
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• 2016

The effect of different thermal treatments on the sub-50 nm copper nanoparticles is examined in the aspects of chemical, electrical and surface morphology. The copper nanoparticles are chemically synthesized and fabricated for paste-type solution. Simple bar coating method is practiced as a deposition process to form copper thin film on a typical slide glass. Deposited copper thin films are annealed by two different routes: general tube furnace with 99.99 % Ar atmosphere and selective laser sintering process. The thermal behavior of the different thermal-treated copper thin films is compared by SEM, XRD, FT-IR and XPS analysis. In this study, the laser sintering process ensures low annealing temperature, fast working speed and ambient-accessible route. Moreover, the laser-sintered copper thin film shows good electrical property and enhanced chemical stability than conventional thermal annealing process. Consequently, the proposed laser sintering process can be compatible with plastic substrate for flexible applications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.29-34
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• 2000

The effects of electrical stress on MILC(Metal Induced Lateral Crystallization) poly-Si TFT were studied. After the electrical stress was applied on the TFT’s which were fabricated by MILC process, off-state(VG<0V) current was reduced by $10^2{\sim}10^4$ times. However, when the device on which electrical stress was applied was annealed in furnace, the off-state current increased as annealing temperature increased. From the dependence of off-state current on the post-annealing temperature, activation energy of the trap states in MILC poly-Si thin films was calculated to be 0.34eV.