• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.211-220
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• 2014

In this paper a full FPGA-based and compact motor-control system is shown that makes it easy to control the motor and analyze the result data in real time with embedding not only a DC motor controller but also a TFT LCD interface in a single FPGA. Both a PID speed control module for a DC motor and a monitoring module for plotting real time graphs on to a TFT LCD are designed in a single FPGA, and the system validity is shown through simulation and experimental results. The FPGA used is xc3s400 and the entire system is designed by using the AD (Altium Designer). A PWM motor drive system is constructed by using MOSFETs for a DC motor 4-quadrant operations.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2363-2369
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• 2014

The DVR system supports multiple cameras and should be able to receive images at 30 frames per channel in real time. Thus, The system is using Full-HD-grade Multiplexer and Hardware compression codec. In this paper, Describing the design and implementation for the 4-channel Full-HD-grade PC-based DVR using FPGA and GPU inside CPU without Multiplexer and Hardware codec. The existing DVR system for Full-HD-grade has drawbacks to acquire images of about only 20 frames per channel in real time. The system to acquire images of multiple channel in real time was designed using FPGA. The software for the system was implemented using Intel Media SDK. At the result of performance evaluation, It was satisfied all for the required conditions. The practicality of the system was confirmed as implementation the system without using hardware compression.

• Journal of IKEEE
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• v.12 no.4
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• pp.239-245
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• 2008

In this paper, a dc-dc power converter scheme with the FPGA based technology is proposed to apply for solar power system which has many features such as the good waveform, high efficiency, low switching losses, and low acoustic noises. The circuit configuration is designed by the conventional control type converter circuit using the isolated dc power supply. This new scheme can be more widely used for industrial power conversion system and many other purposes. Also, I proposed an efficient photovoltaic power interface circuit incorporated with a FPGA based DC-DC converter and a sine-pwm control method full-bridge inverter. The FPGA based DC-DC converter operates at high switching frequency to make the output current a sine wave, whereas the full-bridge inverter operates at low switching frequency which is determined by the ac frequency. As a result, we can get a 1.72% low THD in present state using linear control method. Moreover, we can use stepping control method, we can obtain the switching losses by Sp measured as 0.53W. This paper presents the design of a single-phase photovoltaic inverter model and the simulation of its performance.

• Journal of Broadcast Engineering
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• v.19 no.5
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• pp.616-626
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• 2014

In this paper, we introduce a real-time stereo-to-multiview conversion system using FPGA and GPU. The system is based on two different devices so that it consists of two major blocks. The first block is a disparity estimation block that is implemented on FPGA. In this block, each disparity map of stereoscopic video is estimated by DP(dynamic programming)-based stereo matching. And then the estimated disparity maps are refined by post-processing. The refined disparity map is transferred to the GPU device through USB 3.0 and PCI-express interfaces. Stereoscopic video is also transferred to the GPU device. These data are used to render arbitrary number of virtual views in next block. In the second block, disparity-based view interpolation is performed to generate virtual multi-view video. As a final step, all generated views have to be re-arranged into a single image at full resolution for presenting on the target autostereoscopic 3D display. All these steps of the second block are performed in parallel on the GPU device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1681-1688
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• 2017

In this paper, we implemented a high-speed signal processing hardware system for Color Line Scan Camera using FPGA and Nor-Flash. The existing hardware system mainly processed by high-speed DSP based on software and it was a method of detecting defects mainly by RGB individual logic, however we suggested defect detection hardware using RGB-HSL hardware converter, FIFO, HSL Full-Color Defect Decoder and Image Frame Buffer. The defect detection hardware is composed of hardware look-up table in converting RGB to HSL and 4K HSL Full-Color Defect Decoder with high resolution. In addition, we included an image frame for comprehensive image processing based on two dimensional image by line data accumulation instead of local image processing based on line data. As a result, we can apply the implemented system to the grain sorting machine for the sorting of peanuts effectively.

• Journal of the Korean Society for Nondestructive Testing
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• v.35 no.6
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• pp.389-397
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• 2015

Recently, wave propagation imaging based on laser scanning-generated elastic waves has been intensively used for nondestructive inspection. However, the proficiency of the conventional software based system reduces when the scan area is large since the processing time increases significantly due to unavoidable processor multitasking, where computing resources are shared with multiple processes. Hence, the field programmable gate array (FPGA) was introduced for a wave propagation imaging method in order to obtain extreme processing time reduction. An FPGA board was used for the design, implementing post-processing ultrasonic wave propagation imaging (UWPI). The results were compared with the conventional system and considerable improvement was observed, with at least 78% (scanning of $100{\times}100mm^2$ with 0.5 mm interval) to 87.5% (scanning of $200{\times}200mm^2$ with 0.5 mm interval) less processing time, strengthening the claim for the research. This new concept to implement FPGA technology into the UPI system will act as a break-through technology for full-scale automatic inspection.

• ETRI Journal
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• v.35 no.3
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• pp.448-458
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• 2013

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.

• Journal of Information Processing Systems
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• v.3 no.1
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• pp.16-20
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• 2007

This paper describes the development of the sensor interface and driver program for a point of care (POC) device. The proposed pac device comprises an ARM9 embedded processor and eight-channel sensor input to measure various bio-signals. It features a user-friendly interface using a full-color TFT-LCD and touch-screen, and a bluetooth wireless communication module. The proposed device is based on the system on a programmable chip (SOPC). We use Altera's Excalibur device, which has an ARM9 and FPGA area on a chip, as a test bed for the development of interface hardware and driver software.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.6
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• pp.523-529
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• 2008

In this paper, we proposed mobile LCD module test device on embedded based, when operating the existing LCD, divide flicker clearly in full frame, and configuration so as to support between other CPU interface, MDDI, SPI, 24Bit RGB interface, etc. that is based on a high-speed CPU. In addition, when demand to test about each pixel of LCD, it is possible to change IP design of H/W, FPGA, but proposed system is application possible without other design changing. Proposed system is made smaller and equipped with battery, so secure with mobility for effective test the LCD/OLED module and it is able to test the pattern by the client program, for example exiting picture, mpeg, simple pattern test and test per pixel, scale, rotation, Odd/Even pixel per video, etc. From now on, if integrating with independent test system and it is configured that is able to mutual communication and test, it is expected to reduce consumption of human resources and improve productivity for LCD module test.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.304-310
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• 2017

In this paper, we propose the architecture of an IPM based lane detector for autonomous vehicles to detect and control the driving route along the curved lane. In the IPM image, we divide the area into two fields, Far/Near Field, and the lane candidate region is detected using the Hough transform to perform the matching for the curved lane. In autonomous vehicles, various algorithms must be embedded in the system. To reduce the system resources, we proposed a method to minimize the number of memory accesses to the image and various parameters on the external memory. The proposed circuit has 96% lane recognition rate and occupies 16% LUT, 5.9% FF and 29% BRAM in Xilinx XC7Z020. It processes Full-HD image at a rate of 42 fps at a 100 MHz operating clock.