• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.4
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• pp.798-804
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• 2003

In this paper, We have designed an advanced circuits for controlling the Ink Nozzle of Printer Head We can fully increase the number of nozzle by reducing the number of Input/Output PADs using the proposed new circuit. The proposed circuit is tested with only 20 nozzles to evaluate functional test using FPGA sample chip. The new circuit architecture can be estimated. Full circuit for controlling 320 nozzles was designed and simulated from ASIC full custom methodology, then the circuit was fabricated by applying 3${\mu}{\textrm}{m}$ CMOS process design rule.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.517-530
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• 1994

In this paper, design of small microprocessor unit is implemented using research purpose VHDL and CAD tools by top-down design method. For this, original basic MPU and its pipelining architectures are suggested. Once, design target, instruction sets, architecture are decided, the operation is confirmed by C language simulation, and then the operation is confirmed by checking internal register contents for given inputs in the case of VHDL simulation. Then, design layouts are made by full/semi-custom design methods by research CAD tools and related simulation is implemented. The feasibility of suggested pipelined structure for performance improvement is confirmed by simulation, and related problems and future research directions are discussed. In conclusion, the MPU design methodology is set up and the design change of architecture is possible by this paper.

• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.1-6
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• 1997

This paper describes the design of a network interface controller (NIC) chip which is to be used to support a novel adaptive virtual cut-through routing method for parallel compute systems with direct (i.e., point-to-point) interconnection networks. The NIC chip is designed to provide the interface between a processing node constructed from commercially available microprocessors and another custom-designed router chip, which in turn performs the actual routing of packets to their respective destinations. The NIC, designed using a semi-full-custom VLSi design technique outperform traditional wormhole routing with a minimal amount of hardware overhead. The NIC design has been fully simulated and laid out using a 0.8$\mu\textrm{m}$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.3B
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• pp.362-368
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• 2001

본 논문에서는 두 개의 17비트 오퍼랜드를 radix-4 Booths 알고리즘을 이용하여 곱셈 연산을 수행하는 곱셈기를 설계하고 효율적인 풀커스팀 디자인에 대한 테스트 방법을 제안하였다. 클럭 속도를 빠르게 하기 위하여 2단파이프라인 구조로 설계하고 규칙적인 레이아웃을 위해 4:2 CSA(Carry Save Adder)를 사용하였다. 회로는 LG 반도체의 0.6-um 3-Metal N-well CMOS 공정을 사용하여 칩으로 제작되었다. 새로운 개념의 모듈레벨 고착 고장 모델을 제안하였고 제안한 테스트 방법을 사용하여 관찰해야 하는 노드의 수를 약 88% 줄여 효율적인 고장 시뮬레이션을 수행하였다. 설계된 곱셈기는 9115개의 트랜지스터로 구성되며 코어 부분의 레이아웃 면적은 약 1135*1545 um2 이다. 제작된 칩은 전원접압 5V에서 약 24MHz의 클럭 주파수로 동작한다.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.20 no.6
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• pp.729-734
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• 2011

The full sintering process of zirconia has some extent of shrinkage and the custom abutment design should consider the pre-compensation volume of the shape. In this paper, we concentrated to reveal the asymmetric sintering characteristics. The circular profile of all six samples were measured using the three dimensional coordinate machine. After the full sintering process, the profiles were measured again. The roundness were compared to those of the original shapes and the percent of shrinkage were calculated. On the other hand, surface roughness was also investigated after the full sintering process. The final average surface roughness was improved by the sintering of the machined zirconia surface.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• Current Optics and Photonics
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• v.8 no.5
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• pp.484-492
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• 2024

In response to the difficulty of synchronously obtaining multiwavelength images for fast two-dimensional (2D) temperature measurement, a multispectral framing imaging optical system is designed, based on the segmented-aperture imaging method and asymmetric surface shape. The system adopts a common-aperture four-channel array structure to synchronously collect multiwavelength temperature-field images. To solve the problem of asymmetric aberration caused by being off-axis, a model of the relationship between incident and outgoing rays is established to calculate the asymmetric custom surface. The designed focal length of the optical system is 80 mm, the F-number is 1:3.8, and the operating wavelength range is 0.48-0.65 ㎛. The system is divided into four channels, corresponding to wavelengths of 0.48, 0.55, 0.58, and 0.65 ㎛ respectively. The modulation transfer function value of a single channel lens is higher than 0.6 in the full field of view at 35 lp/mm. The experimental results show that the asymmetric-custom-surface imaging system can capture clear multiwavelength images of a temperature field. The framing imaging system can capture clear images of multiwavelength temperature fields, with high consistency in images of different wavelengths. The designed optical system can provide reliable multiwavelength image data for 2D temperature-field measurement.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.