• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)

• Journal of electromagnetic engineering and science
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• v.16 no.4
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• pp.241-247
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• 2016

This paper proposes the design and measurement of a 6-18 GHz front-end receiver module that has been combined into a one- channel output from a two-channel input for electronic warfare support measures (ESM) applications. This module includes a limiter, high-pass filter (HPF), power combiner, equalizer and amplifier. This paper focuses on the design aspects of reducing the noise figure (NF) and matching the phase and amplitude. The NF, linear equalizer, power divider, and HPF were considered in the design. A broadband receiver based on a combined configuration used to obtain low NF. We verify that our receiver module improves the noise figure by as much as 0.78 dB over measured data with a maximum of 5.54 dB over a 6-18 GHz bandwidth; the difference value of phase matching is within $7^{\circ}$ between ports.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2552-2554
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• 2001

This paper presents a front-end electronic circuits for signal detection on multi-gap resistive plate. The input to the circuit is the signal(voltage : -800mv, frequency : 20${\sim}$40MHZ, noise : 50mv, 1GHz) from the multi-gap resistive plate chamber and the output is the 5v pulse signal. The front-end electronic circuit consists of preamplifier, peak-detector, and comparator. Spice simulation show that the circuit has the better response time than the one of the conventional measuring instruments.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.59-66
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• 1986

A prototype ultrasound sector B-scanner has been developed where the front-end hardware refers to all the necessary circuits for transmitting the ultrasound pulses into the human body and receiving the reflected echo signals from it. The front-end hardware can generally be divided into three parts, i.e., a pulse generator for insonification, a receiver which is responsible for processing of low-level analog signals, and a steering controller for driving the mechanical sector probe whose functions and design concepts are described in this paper. The front-end hardware is implemented which incorporates the following features: improvement of the axial resolution using a circuit which reduces the ring-down time, flexibility of generating time-gain compensation curve, and adoption of a one-chip microcomputer for generating the rate pulses based on the sensor output waveforms.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.7
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• pp.120-126
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• 2001

The widely used spot welded section members of vehicles are structures which absorb most of the energy in a front-end collision. In front-end collision, sufficiently absorbed in the front parts, the impact energy does not reach the passengers. Simultaneously, the frame gets less damaged. This structures have to be very stiff, but collapse progressively to absorb the kinetic energy as expected. In the view of stiffness, the double-hat shaped section member is stiffer than the hat shaped section member. In progress of collapse, the hat shaped section member is collapsing progressively, but the double-hat shaped section member does not due to stiffness. An analysis on the hat shaped section member was previously completed. This paper concerns the collapse characteristic of the double-hat shaped section member. In the program system presented in this study, an explicit finite element code, LS-DYNA3D is adopted for simulating complicate collapse behavior of double hat shaped section members with respect to spot weld pitches. And comparing with the results from the quasi-static and impact experiment, the simulation has been verified.

• Journal of IKEEE
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• v.18 no.1
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• pp.172-178
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• 2014

This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the $SpO_2$ value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a $0.11{\mu}m$ CMOS technology and has 4 level of gain properties. The occupied area is $0.174mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.2
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• pp.23-29
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• 2003

The spot welded sections of automobiles (hat and double hat shaped sections) absorb most of the energy in a front-end collision. The target of this paper is to analyze the energy absorbing capacity of the structure against the front-end collision, and to obtain useful information for designing stage. Changed the spot welded pitches on the flanges, the hat and double hat shaped section members were tested on the axial collapse loads at various impact velocities. It was expected that para-closed sections would show collapse characteristics which be quite different from those of perfectly closed sections. Hat shaped section members were tested at the impact collapse velocities of 4.72m/sec, 6.54m/sec and 7.1m/sec and double hat shaped section members were tested at the impact collapse velocities of 6.54m/sec, 7.1 m/sec and 7.27m/sec.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.300-311
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• 2016

The analog-to-digital-converter-based (ADC-based) backplane receivers that consist of a front-end ADC followed by a digital equalizer are gaining more popularity in recent years, as they support more sophisticated equalization required for high data rates, scale better with fabrication technology, and are more immune to PVT variations. Unfortunately, designing an ADC-based receiver that meets tight power and performance budgets of high-speed backplane link systems is non-trivial as both front-end ADC and digital equalizer can be power consuming and complex when running at high speed. This paper reviews the state of art designs for the front-end ADC and digital equalizers to suggest implementation choices that can achieve high speed while maintaining low power consumption and complexity. Design-space exploration using system-level models of the ADC-based receiver allows through analysis on the impact of design parameters, providing useful information in optimizing the power and performance of the receiver at the early stage of design. The system-level simulation results with newer device parameters reveal that, although the power consumption of the ADC-based receiver may not comparable to the receivers with analog equalizers yet, they will become more attractive as the fabrication technology continues to scale as power consumption of digital equalizer scales well with process.