• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.9
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• pp.1330-1336
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• 2015

It is necessary to study on acoustic and vibratory response of a MEMS resonant accelerometer before applying to military applications. In this paper, we analyze why the resonant accelerometer reacts to an acoustic wave and a high frequency vibration. And we describe experimental results on acoustic and vibratory response of the accelerometer. The accelerometer consists of a proof mass and a dual ended tuning fork. It is a differential resonant accelerometer with arranging a pair of accelerometers. The mode shape was analyzed to find out the input mode frequency by using a FEM simulation. Some experiments regarding the acoustic noise was carried out by using a tweeter and a microphone in the anechoic room. Results showed that the accelerometer reacted to the acoustic wave and vibration which had the input mode frequency as we had expected. We showed experimentally not only that the susceptibility of the accelerometer to an acoustic wave was 70 dB but also that the effectiveness of applying an acoustic absorber and a metal case was 20 dB, respectively. Also, we could minimize the vibratory response property of the accelerometer by installing a IMU with a silicone rubber mount pad.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.1-9
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• 2010

This paper describes a ultrasonic signal processing front-end IC for distance range meter and body detector. The burst shaped ultrasonic signal is generated by a self oscillator and its frequency range is about 40[kHz]-300[kHz]. The generated ultrasonic signal transmit through piezo resonator. The another piezo device transduce from received ultrasonic signal to electrical signals. This front-end IC contained low noise amplifier, band pass filter, busrt detector and time pulse generator and so on. This IC has two type of new idea for improve function and performance, which are self frequency control (SFC) and Variable Gain Control amplifier (VGC) scheme. The dimensions and number of external parts are minimized in order to get a smaller hardware size. This device has been fabricated in a O.6[um] double poly, double metal 40[V] High Voltage CMOS process.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.57-63
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• 2016

This paper describes implementation of the RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4g SUN sensor node transceiver modules. Design of the each module like VCO, prescaler, 1/N divider, ${\Delta}-{\Sigma}$ modulator, and common circuits of the PLL has been optimized to obtain high speed and low noise performance. Especially, the VCO has been designed with NP core structure and 13 steps cap-bank to get high speed, low noise, and wide band tuning range. The output frequencies of the implemented synthesizer is 1483MHz~2017MHz, the phase noise of the synthesizer is -98.63dBc/Hz at 100KHz offset and -122.05dBc/Hz at 1MHz offset.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.49-54
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• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.6
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• pp.87-93
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• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• Journal of Power System Engineering
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• v.3 no.3
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• pp.60-69
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• 1999

The noise and vibration sources of rotary compressor for room air-conditioner are pressure pulsation of compression process, cavity resonance of inner space, structural radiation noise of shell and impact noise of discharge valve. Among them, pressure pulsation is very important noise and vibration source. Because it transferred various kinds of noise and vibration like as mentioned above. In this reason, muffler and resonator are used in order to absorb and remove these noises. But an analytical prediction using acoustic analysis does not coincident with the experimental result. The difference between analysis and actual state is due to the assumption of analysis. This paper covered with new concept of muffler design based on the turbulence kinetic energy of flow by using CFD. From this analysis, it is possible to decide the best position of discharge port of muffler. Therefore $2{\sim}3dB$ noise reduction effect is acquired in rotary compressor of 5000 BTU grade. Also new approach of resonator design is suggested. From this study, the characteristics of resonator and surge hole (a kind of resonator without pipe length) are identified. The former is useful for pure tone noise (narrow frequency band), and the latter is effective for broad frequency band. This paper shows that it is very available to use 3 dimensional analysis of resonator in order to predict more exact tuning frequency. The result is proved by a lot of experiments. From combination of fluid analysis and acoustic analysis, up stream position is effective location of resonator concerning turbulence motion of fluid.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.6
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• pp.805-814
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• 1999

In this paper, elliptic function bandpass filters using ceramic coaxial resonators are designed. Since elliptic function filters have better performance of frequency selectivity than those based on Butterworth or Chebyshev, therefore it is possible to make better use of limited frequency resources. Elliptic function bandpass filters using ceramic coaxial resonators are designed for reducing it's size, weight, cost and for easy manufacturing and tuning. From measurements, an accurate resonator model is obtained and the coupling coefficient values are extracted. Based on these results, elliptic function bandpass filters are designed. The experimental results have shown that the 8th order elliptic function filter of 959 MHz center frequency with 28 MHz bandwidth using coaxial ceramic resonators have about more tan 17 dB return loss, 5 dB insertion loss, more than 20 dB attenuation at $f_c\pm$5 MHz.

• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.36-42
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• 2008

Implementation of a wavelength-swept source with constant tuning rate adopting a PZT-type tunable filter, requires the knowledge of hysteresis of the filter used. The hysteresis must be considered to avoid any degradation in resolution of the optical frequency domain reflectometry (OFDR) system. An optical spectrum analyzer (OSA) could be used to do the hysteresis measurement, but its measurement time is too long for the high-speed driving conditions for the filter. We proposed a new hysteresis measurement method based on OFDR, which could measure the hysteresis in a real driving condition. A hysteresis measurement apparatus consisted of wavelength-swept source, interferometer, signal processing unit, and PC program is built and used to do the measurement. It is concluded that the new method is useful in the measurement of hysteresis at real driving conditions by successfully implementing a swept-wavelength source whose wavelength change is linear in time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.5
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• pp.1125-1134
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• 2011

In this paper a wideband frequency synthesizer is designed for DTV tuners using a $0.18{\mu}m$ CMOS process. It satisfies the DTV frequency band(48~1675MHz). A scheme is proposed to cover the full band using only one VCO and reliable broadband characteristics are achieved by reducing the variations of VCO gains and frequency steps. The simulation results show that the designed VCO has frequency range of 1.85~4.22GHz, phase noise at 4.22GHz of -89.7dBc/Hz@100kHz, gains of 62.4~95.8MHz/V(${\pm}21.0%$) and frequency steps of 22.9~47.9MHz(${\pm}35.3%$). The designed VCO has a phase noise of -89.75dBc/Hz at 100kHz offset. The designed synthesizer has a lock time less than $0.15{\mu}s$. The measured VCO tuning range is 2.05~3.4GHz. The frequency range is shifted down but still satisfy the target range owing to the design for enough margin. The designed circuit consumes 23~27mA from a 1.8V supply, and the chip size including PADs is $2.0mm{\times}1.5mm$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.