• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.294-297
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• 2003

This paper describes the design and the simulation of a frequency doubler for millimeter-wave applications using distributed amplifier technology. The designed frequency multiplier has 10% bandwidth at 58GHz output. This paper investigates nonlinear analysis of pHEMT frequency multipliers utilizing AM-AM and AM-PM distortion characteristics of frequency doubler. The conversion loss is 2.1dB and harmonic suppression is larger than 18.6dBc with 5dBm input power

• Journal of electromagnetic engineering and science
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• v.7 no.4
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• pp.175-182
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• 2007

In this paper, a study on the reflector type frequency doubler, to suppress the undesired harmonics, is presented. A 12 to 24 GHz reflective frequency doubler is simulated and experimented. Design procedure of the frequency doubler with reflector is provided and the frequency doubler with good spectral purity is fabricated successfully. It has harmonic suppression of the $40{\sim}50\;dBc$ in the $1^{st}$ harmonic and the $50{\sim}60\;dB$ in the $3^{rd}$ harmonic with no additional filter. And, it has conversion gain with the input power of 0 dBm over bandwidth of 500 MHz. A NEC's ne71300(N) GaAs FET is used and the nonlinear model(EEFET3) using IC-CAP program is extracted for harmonic load pull simulation. Good agreement between simulated and measured results has been achieved.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.560-566
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• 2004

In this paper, active frequency doubler with broadband characteristics from 6 ㎓ to 12 ㎓ was designed and fabricated using PHEMT. The designed frequency multiplier has a bias point near pinch-off and a proposed series RC circuit between bias line and input matching network far the improvement of stability. With 0 ㏈m input power, second harmonic of 1.7 ㏈m at 12 ㎓ -27.5 ㏈c suppression of 6 ㎓ fundamental, -18 ㏈c suppression of 18 ㎓ 3rd harmonic, and the 3 ㏈ output bandwidth of 1,8 ㎓ have been measured.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.342-345
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• 2014

An active frequency doubler monolithic microwave integrated circuit (MMIC) for E-band transceiver applications is presented in this letter. This MMIC has been fabricated in a commercial $0.1-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (pHEMT) process on a 2-mil thick substrate wafer. The fabricated MMIC chip has been measured to have a high output power performance of over 13 dBm with a high fundamental leakage suppression of more than 38 dBc in the frequency range of 71 to 86 GHz under an input signal condition of 10 dBm. A microstrip coupled line is used at the output circuit of the doubler section to implement impedance matching and simultaneously enhance the fundamental leakage suppression. The fabricated chip is has a size of $2.5mm{\times}1.2mm$.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.49-55
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• 2015

This paper proposes a 2.4 GHz RF oscillator with a very low close-in phase noise performance. This is composed of a low frequency crystal oscillator and three frequency multipliers such as two doubler (X2) and one tripler (X3). The proposed oscillator is implemented as a hybrid type circuit design using a discrete silicon bipolar transistor. The measurement results of the proposed oscillator structure show -115 dBc/Hz close-in phase noise at 10 kHz offset frequency, while only dissipating 5 mW from a 1-V supply. Its close-in phase noise level is very close to that of a low frequency crystal oscillator with little degradation of noise performance. The proposed structure which is consisted of a low frequency crystal oscillator and a frequency multiplier provides new method to implement a low power low close-in phase noise RF local oscillator.

• Journal of electromagnetic engineering and science
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• v.14 no.1
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• pp.25-30
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• 2014

This paper discusses the design of a high frequency Greinacher voltage multiplier as rectifier; it has a greater conversion efficiency and higher output direct current (DC) voltage at high power compared to a simple halfwave rectifier. Multiple diodes in the Greinacher voltage multiplier with distributed circuits consume excited power to the rectifier equally, thereby increasing the overall power capacity of the rectifier system. The proposed rectifiers are a Greinacher voltage doubler and a Greinacher voltage quadrupler, which consist of only diodes and distributed circuits for high frequency applications. For each rectifier, the RF-to-DC conversion efficiency and output DC voltage for each input power and load resistance are analyzed for the maximum conversion efficiency. The input power with maximum conversion efficiency of the designed Greinacher voltage doubler and quadrupler is 3 and 7 dB higher, respectively;than that of the halfwave rectifier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.148-153
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• 2011

In this paper, an inverse class E frequency multiplier has been designed to generate 5.8 GHz wireless LAN signal by multiplying 2.9 GHz input. The inverse class E frequency multiplier is operating with low inductance value and low peak drain voltage than the class E frequency multiplier. Measurement shows the output power of 21 dBm, the mutiplier gain of 6 dB, and the PAE(Power Added Efficiency) of 35 % with 15 dBm input power.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.213-219
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• 2007

In this paper, A novel structure of frequency doubler using Phase Delay line and $90^{\circ}$ Hybrid coupler at harmonic output have been designed and implemented to improve suppression. Proposed structure of frequency doubler improve output. coupling and fundamental suppression. Active frequency doubler with band from $2.13{\sim}2.15GHz\;to\;4.26{\sim}4.3GHz$ was designed and fabricated with 10dBm input power, 0.79dB conversion gain and -55.54dBc suppression at fundamental frequency, -44.76dBc suppression at third harmonic frequency 6.42GHz and -39.18dBc suppression at fourth harmonic frequency 8.56GHz.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.596-601
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• 2011

This paper has presented research results for the switching mode class E frequency multiplier that has simple circuit structure and high efficiency. Frequency multiplication is coming from the nonlinearity of the active component, and this paper models the FET active component as a simple switch and some parasitics to analyze the characteristics. The matching component parameters for the class E frequency doubler have been derived with modeling the FET as a input controlled switch and some parasitics. A circuit simulator, ADS, is used to simulate the output voltage and current waveform and efficiency with the variation of the parasitic values. With 2.9GHz input and 2V bias, the drain efficiency has been decreased from 98% to 28% with changing the parasitic capacitance from 0pF to 1pF at 5.8GHz output, which shows that the parasitic capacitance CP has the most significant effect on the efficiency among the parasitics of FET.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.127-132
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• 2006

This paper presents a dual-mode amplifier which operates as amplifier or frequency multiplier according to the input frequency. It satisfies the 802.11a/b/g frequency band of wireless LAN standard. A conventional dual-band wireless LAN transmitter consists of the separating power amplifiers operating at each frequency band, but the proposed dual-mode amplifier operates as an amplifier for the 802.11b/g signal and as a frequency multiplier for the 802.11a signal according to each LAN bias condition. The amplifier mode shows the gain of 13dB, the PldB of 17dBm and second harmonic suppression of below -37dBc. And the frequency-doubler mode shows the gain of 3.3dB, the output power of 7.3dBm and third harmonic suppression of below -50dBr.