• Title/Summary/Keyword: Frequency locking

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Isogeometric method based in-plane and out-of-plane free vibration analysis for Timoshenko curved beams

  • Liu, Hongliang;Zhu, Xuefeng;Yang, Dixiong
    • Structural Engineering and Mechanics
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    • v.59 no.3
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    • pp.503-526
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    • 2016
  • In-plane and out-of-plane free vibration analysis of Timoshenko curved beams is addressed based on the isogeometric method, and an effective scheme to avoid numerical locking in both of the two patterns is proposed in this paper. The isogeometric computational model takes into account the effects of shear deformation, rotary inertia and axis extensibility of curved beams, and is applicable for uniform circular beams, and more complicated variable curvature and cross-section beams as illustrated by numerical examples. Meanwhile, it is shown that, the $C^{p-1}$-continuous NURBS elements remarkably have higher accuracy than the finite elements with the same number of degrees of freedom. Nevertheless, for in-plane or out-of-plane vibration analysis of Timoshenko curved beams, the NURBS-based isogeometric method also exhibits locking effect to some extent. To eliminate numerical locking, the selective reduced one-point integration and $\bar{B}$ projection element based on stiffness ratio is devised to achieve locking free analysis for in-plane and out-of-plane models, respectively. The suggested integral schemes for moderately slender models obtain accurate results in both dominated and non-dominated regions of locking effect. Moreover, this strategy is effective for beam structures with different slenderness. Finally, the influence factors of structural parameters of curved beams on their natural frequency are scrutinized.

Design of Frequency Synthesizer Using VCO Multi-Phase Signals (VCO 위상신호를 이용한 주파수 합성기 설계)

  • 이준호;김선홍;김종민;박창선;김동용
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.978-981
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    • 1999
  • In this paper, an improved integer-N frequency synthesizer that can be synthesized into smaller channel space than input signal frequency is presented. The proposed frequency synthesizer also has an characteristics of fast phase locking time. The frequency synthesizer performed in the manner that it divides various outputs of different phases in VCO by means of dividers that have different control signals respectively and then add the divided signal. In order to confirm the characteristics of proposed frequency synthesizer, behavioral and SPICE simulations are performed using C-language and HSPICE respectively.

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A Study on the Design of PLL for Improving of Characteristics of Locking Time and Jitter (Locking Time과 Jitter 특성의 개선을 위한 PLL 설계에 관한 연구)

  • Park, Jae-Boum;Park, Yun-Sik;Kim, Hwa-Young;Sung, Man-Young
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2003.07b
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    • pp.1188-1191
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    • 2003
  • In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.

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Spontaneous Oscillatory Rhythm in Retinal Activities of Two Retinal Degeneration (rd1 and rd10) Mice

  • Goo, Yong-Sook;Ahn, Kun-No;Song, Yeong-Jun;Ahn, Su-Heok;Han, Seung-Kee;Ryu, Sang-Baek;Kim, Kyung-Hwan
    • The Korean Journal of Physiology and Pharmacology
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    • v.15 no.6
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    • pp.415-422
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    • 2011
  • Previously, we reported that besides retinal ganglion cell (RGC) spike, there is ~10 Hz oscillatory rhythmic activity in local field potential (LFP) in retinal degeneration model, rd1 mice. The more recently identified rd10 mice have a later onset and slower rate of photoreceptor degeneration than the rd1 mice, providing more therapeutic potential. In this study, before adapting rd10 mice as a new animal model for our electrical stimulation study, we investigated electrical characteristics of rd10 mice. From the raw waveform of recording using $8{\times}8$ microelectrode array (MEA) from in vitro-whole mount retina, RGC spikes and LFP were isolated by using different filter setting. Fourier transform was performed for detection of frequency of bursting RGC spikes and oscillatory field potential (OFP). In rd1 mice, ~10 Hz rhythmic burst of spontaneous RGC spikes is always phase-locked with the OFP and this phase-locking property is preserved regardless of postnatal ages. However, in rd10 mice, there is a strong phase-locking tendency between the spectral peak of bursting RGC spikes (~5 Hz) and the first peak of OFP (~5 Hz) across different age groups. But this phase-locking property is not robust as in rd1 retina, but maintains for a few seconds. Since rd1 and rd10 retina show phase-locking property at different frequency (~10 Hz vs. ~5 Hz), we expect different response patterns to electrical stimulus between rd1 and rd10 retina. Therefore, to extract optimal stimulation parameters in rd10 retina, first we might define selection criteria for responding rd10 ganglion cells to electrical stimulus.

Charge Pump PLL for Lock Time Improvement and Jitter Reduction (Lock Time 개선과 Jitter 감소를 위한 전하 펌프 PLL)

  • Lee, Seung-Jin;Choi, Pyung;Shin, Jang-Kyoo
    • Proceedings of the IEEK Conference
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    • 2003.07c
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    • pp.2625-2628
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    • 2003
  • Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1%, and the jitter is reduced by 45.2% compared with typical CPPLL.

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Fabrication and Output Characteristics of a High-Speed Wavelength Swept Mode-Locked Laser (고속 파장가변 모드잠김 레이저의 제작 및 출력특성)

  • Lee, Eung-Je;Kim, Yong-Pyung
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.6
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    • pp.1117-1121
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    • 2007
  • We demonstrate a wavelength swept mode-locked ring laser for the frequency domain optical coherence tomography(FD OCT). A laser is constructed by using a semiconductor optical amplifier, fiber Fabry-Perot tunable filter and 2.6 km fiber ring cavity. Mode-locking is implemented by 2.6 km fiber ring cavity for matching the fundamental or harmonic of cavity roundtrip time to a sweep period. The wavelength sweeps are repetitively generated with the repetition period of 77.2 kHz which is the parallel resonance frequency of Fabry-Perot tunable filter for the low driving current consumption of the fiber Fabry-Perot tunable filter. The wavelength tuning range of the laser is more than FWHM of 61 nm centered at the wavelength of 1320 nm and the linewidth of the source is $0.014{\pm}0.002$ nm.

A design of PLL for low jitter and fast locking time (빠른 고정 시간과 작은 지터를 갖는 PLL의 설계)

  • Oh, Reum;Kim, Doo-Gon;Woo, Young-Shin;Sung, Man-Young
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.3097-3099
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    • 2000
  • In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

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A Study on the RF Shower System to Extend Interrogating Range for the Low Power RFID Reader System (저출력 RFID 시스템에서 인식거리 확대를 위한 전력 공급용 RF Shower 시스템)

  • Jung, Jin-Wook;Bae, Jae-Hyun;Oh, Ha-Ryoung;Seong, Yeong-Rak;Song, Ho-Jun;Jang, Byeong-Jun;Choi, Kyung;Lee, Jung-Suk;Lee, Hong-Bae;Lee, Hak-Yong;Kim, Jong-Min;Shin, Jae-Cheol;Park, Jun-Seok
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.55 no.12
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    • pp.526-533
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    • 2006
  • In this paper, we presented the synchronization module between RF shower system and RFID Reader to extend interrogating range on Mobile RFID system, Costas Loop and FPLL(Frequency/phase Lock Loop) were used. We achieved compromised range of 3MHz locking frequency, 1ms locking time and figured out remarkable Hopping frequency of the Reader. The prototype of the new designed RFID system has been tested with ISO18000-6 type-B Tag. The read range between designed RFID Reader and Tag has been measured, it increased triple times by adjusting the Shower system output level.

A Design of Voltage Controlled Oscillator and High Speed 1/4 Frequency Divider using 65nm CMOS Process (65nm CMOS 공정을 이용한 전압제어발진기와 고속 4분주기의 설계)

  • Lee, Jongsuk;Moon, Yong
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.107-113
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    • 2014
  • A VCO (Voltage Controlled Oscillator) and a divide-by-4 high speed frequency divider are implemented using 65nm CMOS technology for 60GHz wireless communication system. The mm-wave VCO was designed by NMOS cross-coupled LC type using current source. The architecture of the divide-by-4 high speed frequency divider is differential ILFD (Injection Locking Frequency Divider) with varactor to control frequency range. The frequency divider also uses current sources to get good phase noise characteristics. The measured results show that the VCO has 64.36~67.68GHz tuning range and the frequency divider divides the VCO output by 4 exactly. The high output power of 5.47~5.97dBm from the frequency divider is measured. The phase noise of the VCO including the frequency divider are -77.17dBc/Hz at 1MHz and -110.83dBc/Hz at 10MHz offset frequency. The power consumption including VCO is 38.4mW with 1.2V supply voltage.

A study on the Frequency control of HF Synthesizer using a Phase-Locked Loop (PLL을 이용한 HF 대 합성기의 주파수 조정에 관한 연구)

  • Song, Weon-Yong;Kim, Kyung-Gi
    • Proceedings of the KIEE Conference
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    • 1987.11a
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    • pp.86-89
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    • 1987
  • This paper treats with the design and fabrication of a frequency synthesizer for the generation of intermediate frequency of a HF band transceiver. The synthesizer is designed to control frequencies using a phase-locked loop and it is shown that method improved the performance of frequency accuracy and locking time then that of the crystal-reference system.

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