• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.129-132
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• 2008

The generally six-port phase correlator is comprised of a wilkinson power divider and three $90^{\circ}$ hybrid coupler, got bandwidth performance of less than 10%. in this paper, the six-port phase correlator using two section power divider has 33% bandwidth and external matching hybrid coupler has 15% bandwidth was designed with the center frequency of 2.5GHz. Analysis of the simulation result indicates that RF port and LO port got frequency bandwidth of 13%. Insert loss performance of fabricated six-port phase correlator is incremented, but bandwidth resembles simulation result. And phase tolerance within bandwidth is less than $90^{\circ}$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.23-28
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• 2009

The general six-port phase correlator is comprised of a Wilkinson power divider and three $90^{\circ}$ hybrid coupler, which has less than 10 % bandwidth. In this paper, the six-port phase correlator using two section power divider has 33 % bandwidth and external matching $90^{\circ}$ hybrid coupler with 15 % bandwidth was designed at the center frequency of 2.5 GHz. The simulation result by ADS2003A indicates that RF port and LO port of proposed six-port phase correlator got wide frequency bandwidth of 14 % for VSWR of 1.5. The fabricated six-port phase correlator has a bandwidth of 12 % similar to the simulation result. The maximum phase discrepancy and insertion loss are $6^{\circ}$ and 2.5 dB over a bandwidth, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.184-184
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• 2008

In this paper, a power divider with a multi-band and broadband are designed and fabricated using an InGaP/GaAs process. The design of this divider is based on multi-band because it is important in the next generation IMT-Advances system. In this design, power divider is fabricated with the frequency of 824 MHz to 894 MHz, 1.8 GHz to 2.2 GHz and 2.3 GHz to 2.4 GH for cellular, personal communication system (PCS) and Wireless Broadband Internet (WiBro). The topology of the designed power divider is based on the multi-section and fabricated using integrated passive device (IPD) library of nanoENS Inc. It is measured using network analyzer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.107-116
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• 2012

In this paper, the trade-off related to bandwidth of high-speed common-mode logic frequency divider is analyzed in detail. A method to optimize the operating frequency, band-width as well as power consumption is proposed. This method is based on bipolar device characteristics, whereby a negative resistance model can be used to estimate the optimal normalized upper frequency and lower frequency of frequency dividers under different conditions, which is conventionally ignored in literatures. This method provides a simple but efficient procedure in designing high performance frequency dividers for different applications. To verify the proposed method, a static divide-by-2 at millimeter wave ranges is implemented in 180 nm SiGe technology. Measurement results of the divider demonstrate significant improvement in the figure of merit as compared with literatures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.941-947
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• 2017

This paper reports a fractional-N phase-locked-loop(PLL) frequency synthesizer that is implemented in a $0.35-{\mu}m$ standard CMOS process and generates a quadrature signal for an FRS terminal. The synthesizer consists of a voltage-controlled oscillator(VCO), a charge pump(CP), loop filter(LF), a phase frequency detector(PFD), and a frequency divider. The VCO has been designed with an LC resonant circuit to provide better phase noise and power characteristics, and the CP is designed to be able to adjust the pumping current according to the PFD output. The frequency divider has been designed by a 16-divider pre-scaler and fractional-N divider based on the third delta-sigma modulator($3^{rd}$ DSM). The LF is a third-order RC filter. The measured results show that the proposed device has a dynamic frequency range of 460~510 MHz and -3.86 dBm radio-frequency output power. The phase noise of the output signal is -94.8 dBc/Hz, and the lock-in time is $300{\mu}s$.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.7 no.3
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• pp.528-537
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• 1995

Natural convective flow and heat transfer characteristics in a partially opened enclosure fitted with a horizontal divider are investigated numerically. The enclosure is composed of a lower hot and a upper cold horizontal walls and adiabatic vertical walls. A divider is attached perpendicularly to the vertical insulated wall. The governing equations are solved by using the finite element method with Galerkin method. The computations have been carried out by varying the length of divider, the opening size, and the Rayleigh number based on the temperature difference between two horizontal walls and the enclosure height for air(Pr=0.71). As result, when the opening size is fixed, the intensity of the secondary flow is weaken as the length of divider increases. The maximum heat transfer rate over the upper cold wall occurs at a position bounded on the opening. However, when the length of divider is increased considerably, its maximum occurs at the right wall. The stability and frequency of oscillation are affected by the Rayleigh number and length of divider. The Nusselt number is increased with the increase of the opening size and the increase of Rayleigh number.

• Journal of electromagnetic engineering and science
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• v.4 no.4
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• pp.150-155
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• 2004

Universal design equations are presented for the H-plane T-junction power divider with a circular conducting post in a rectangular waveguide. For a given operating frequency and power split ratio, the post offset from the T-junction center line, the distance between the post and the waveguide wall, and the post diameter can be adjusted to obtain a minimum reflection at the input waveguide. Optimum values of the post offset are given in terms of the normalized frequency and the power split ratio. Corresponding values of the post diameter and the distance of the post from the waveguide wall are given in terms of the normalized frequency and the post offset.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.4
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• pp.651-658
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• 2001

A novel multi-section power divider configuration is proposed to obtain wide-band frequency performance up to microwave frequency region. Design procedures for the proposed microwave broadband power divider are composed of a planar multi-section three-ports hybrid and a waveguide transformer design procedures. The multi-section power divider is based on design theory of the optimum quarter-wave transformer. Furthermore, in order to obtain the broadband isolation performance between the two adjacent output ports, the odd mode equivalent circuit should be matched by using the lossy element such as resistor. The derived design formula for calculating these odd mode matching elements is based on the singly terminated filter design theory. The waveguide transformer section is designed to suppress the propagation of the higher order modes such as waveguide modes due to employing the metallic electric wall. Thus, each section of the designed waveguide transformer should be operated with evanescent mode over the whole design frequency band of the proposed microwave broadband power divider. This paper presents several simulations and experimental results of multi-section power divider to show validity of the proposed microwave broadband power divider configuration. Simulation and experiment show excellent performance of multi section power divider.

• Journal of electromagnetic engineering and science
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• v.12 no.3
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• pp.216-222
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• 2012

This paper presents a single-pole eight-throw switch, based on an eight-way power divider, using substrate integrate waveguide(SIW) technology. Eight sectorial-lines are formed by inserting radial slot-lines on the top plate of SIW power divider. Each sectorial-line can be controlled independently with high level of isolation. The switching is accomplished by altering the capacitance of the varactor on the line, which causes different input impedances to be seen at a central probe to each sectorial line. The proposed structure works as a switching circuit and an eight-way power divider depending on the bias condition. The change in resonant frequency and input impedance are estimated by adapting a tapered transmission line model. The detailed design, fabrication, and measurement are discussed.