• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.281-286
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• 2007

In this paper, sub-circuits for 24 GHz phase locked 100ps(PLLs) using $0.5{\mu}m$ SiGe HBT are presented. They are 24 Ghz voltage controlled oscillator(VCO), 24 GHz to 12 GHz regenerative frequency divider(RFD) and 12 GHz to 1.5 GHz static frequency divider. $0.5{\mu}m$ SiGe HBT technology, which offers transistors with 90 GHz fMAX and 3 aluminum metal layers, is employed. The 24 GHz VCO employed series feedback topology for high frequency operation and showed -1.8 to -3.8 dBm output power within tuning range from 23.2 GHz to 26 GHz. The 24 GHz to 12 GHz RFD, based on Gilbert cell mixer, showed 1.2 GHz bandwidth around 24 GHz under 2 dBm input and consumes 44 mA from 3 V power supply including I/O buffers for measurement. ECL based static divider operated up to 12.5 GHz while generating divide by 8 output frequency. The static divider drains 22 mA from 3 V power supply.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.2
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• pp.85-91
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• 2002

A novel multi-section power divider configuration is Proposed to obtain wide-band frequency performance up to microwave frequency region. Design procedures for the proposed microwave broadband power divider are composed of a Planar multi-section three-Ports hybrid and a waveguide transformer design procedures. The multi∼section power divider is based on design theory of the optimum quarter- wave transformer Furthermore, in order to obtain the broadband isolation performance between the two adjacent output ports, the odd mode equivalent circuit should be matched by using the lossy element such as resistor. The derived design formula for calculating these odd mode∼matching elements is based on the singly terminated filter design theory. The waveguide transformer section is designed to suppress the propagation of the higher order modes such as waveguide modes due to employing the metallic electric wall. Simulation and experiment show excellent performance of multi section power divider.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.1
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• pp.54-62
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• 1988

For code division multiple access, a frequency synthesizer of elementary components is necessary in the system application of frequency hopped spread spectrum communication. This paper proposes the model of N-loop PLL frequency synthesizer to be adaptied for generating the output frequency resultes in the frequency hopping pattern and to be easy in practical application of the system. It was analyzed how the frequency divider ratio distribute, what the method to decide frequency divider ratio is and what relationship of bandwidth of BPF and degree of multiple have is also analyzed in order to hop the desired frequency output.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.620-624
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• 2016

In this paper we designed a current mode logic frequency divider to transmit a baseband amplitude modulated signal. From simulation result, we studied input and output waveforms according to the variation of input bias voltage. For the purpose of the verification of the study, we designed a current mode logic frequency divider at 1,400 MHz. The designed frequency divider operates between 100 MHz and 3,000 MHz, for -33 dBm input power. The circuit draws $I_{total}=30mA$ from $V_{DD}=3V$ supply, and the simulation result shows that an amplitude modulated signal at 1,400 MHz with the modulation index of 0.5 was successfully downconverted to 700 MHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.1
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• pp.384-389
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• 2011

This article presents an ultra broadband resistive power divider circuit for smart grid applications. Since the future smart grid system is expected to deploy high speed power line communication, the frequency response of the resitive power divider circuit is naturally of significance. Employing a thin film technology, the resistive power divider was designed, measured, and fabricated. For the circuit design, the conductor-backed coplanar waveguide line was firstly designed and measured. The 3 dB cutoff frequency was 72 GHz and S11 remains <-20 dB upto 70 GHz. The fabricated resistive power divider shows the 3 dB cutoff frequency of 50 GHz. It was experimentally verified that the resistive power divider circuit shows the insertion loss of 6 dB for high-speed input signal (40 Gb/s).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.500-505
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• 2002

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed frequency divider has designed in a standard 0.25$\mu\textrm{m}$ CMOS technology. To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65$\mu\textrm{m}$ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz, a tuning range of ${\pm}$10%, and a gain of 154MHz/V. The simulated frequency synthesizer performance has a settling time of 1.5${\mu}\textrm{s}$, a frequency range from 820MHz to 1GHz and power consumption of 70mW at 2.5V power supply voltage.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.208-211
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• 2000

This paper describes the design of a CMOS frequency synthesizer using programmable frequency divider with novel architecture. A novel architecture of programmable divider can be producted all of integer-N and fabricated by 0.65$\mu\textrm{m}$ 2-poly, 2-metal CMOS technology. Frequency synthesizer is simulated by 0.25$\mu\textrm{m}$ 2-poly, 5-metal CMOS technology. This circuit has settling time of 1.5${\mu}\textrm{s}$ and power consumption of 70㎽. Operating frequency of the frequency synthesizer is 820MHz∼l㎓ with a 2.5V supply voltage.

• Journal of Advanced Navigation Technology
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• v.20 no.1
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• pp.59-64
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• 2016

This paper presents a high dividing ratio unequal dualband divider using coplanar waveguide (CPW) and shunt connected open stub transmission lines. In order to implement transmission lines for a dualband divider using design equations, the low impedance lines of divider can be realized a shunt connected open stub transmission line. Also, the high impedance lines are realized by CPW transmission lines. To certify the validity of an unequal dualband divider using CPW and shunt connected open stub transmission lines, the 10:1 unequal dualband divider is implemented at operating frequency of 1 and 2 GHz. Good experimental performance at each frequency are obtained, which are in good agreement with the simulated results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.9
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• pp.1727-1732
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• 2011

In order to realize a high performance(low loss, high isolation) microwave power divider/combiner, we have designed the power combiner/divider precisely in accordance with the different hight of central part. In the case of the high central part of the hight of $h_r$=10.2, a compensating part of the conical line is inserted in the conical conversion transmission line, and in the case of low central part of the hight of $h_r$=5.0, the conical conversion transmission line is remodeled into the 2-stage bend structure. In both case, the reflection characteristics are improved to 30dB over the operating frequency range of 5GHz bandwidth. A resistance is inserted between the peripheral ports so as to try to improve the isolation characteristics of the device. For the 16-divider/combiner, the isolation characteristics are improved to 10dB over the operating frequency range of 5GHz bandwidth.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1829-1831
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• 2001

A novel multi-section power divider configuration is proposed to obtain wide-band frequency performance up to microwave frequency region. Design procedures for the proposed microwave broadband power divider are composed of a planar multi-section three-ports hybrid and a waveguide transformer design procedures. The multi-section power divider is based on design theory of the optimum quarter-wave transformer. Furthermore, in order to obtain the broadband isolation performance between the two adjacent output ports, the odd mode equivalent circuit should be matched by using the lossy element such as resistor. The derived design formula for calculating these odd mode matching elements is based on the singly terminated filter design theory. The waveguide transformer section is designed to suppress the propagation of the higher order modes such as waveguide modes due to employing the metallic electric wall. Simulation and experiment show excellent performance of multi section power divider.