• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.941-944
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• 2015

In this paper study for VSAT(very small aperture terminal) LNB(low noise block). ship LNB was demanded high stability and low noise figure. We designed FEM(Front-End Module) that was operated multi-band. FEM designed was constructed in a multi-band low noise receiver amplifier, a frequency converter, IF amplifier, Voltage Control Oscillator signal generating circuit four circuit using. To convert the multi-band 2.05GHz band, it generates four local oscillator signals, the four(band1, band2, band3, band4) designed to output an IF signal developed conversion apparatus, the conversion gain 64dB, noise figure 1dB or less, output P1dB 15dBm or more, phase noise showed -73dBc@100Hz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.60-67
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• 2010

We designed Average Current Control PFC IC which has make the average value of boost inductor current became the shape of sine wave. Designed IC has fixed frequency of 75kHz to meet EMI standard requirement. And also RC compensation loop has been designed into the error amp and the current amp, in order that it has wide bandwidth for high speed control. And we use the oscillator which generates by square wave and triangle wave, and add to UVLO, OVP, OCP, TSD which is in order to operate stability. We simulated by using Spectre of Cadence to verify the unity power factor function and various protection circuits and fabricated in a $1{\mu}m$ High Voltage(20V) CMOS process.

• Journal of Power Electronics
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• v.15 no.1
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• pp.190-201
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• 2015

This paper uses the switching function approach to present a simple state model of the Vienna-type rectifier. The approach introduces the relationship between the DC-link neutral point voltage and the AC side phase currents. A novel direct power control (DPC) strategy, which is based on the sliding mode control (SMC) for Vienna I rectifiers, is developed using the proposed power model in the stationary ${\alpha}-{\beta}$ reference frames. The SMC-based DPC methodology directly regulates instantaneous active and reactive powers without transforming to a synchronous rotating coordinate reference frame or a tracking phase angle of grid voltage. Moreover, the required rectifier control voltages are directly calculated by utilizing the non-linear SMC scheme. Theoretically, active and reactive power flows are controlled without ripple or cross coupling. Furthermore, the fixed-switching frequency is obtained by employing the simplified space vector modulation (SVM). SVM solves the complicated designing problem of the AC harmonic filter. The simplified SVM is based on the simplification of the space vector diagram of a three-level converter into that of a two-level converter. The dwelling time calculation and switching sequence selection are easily implemented like those in the conventional two-level rectifier. Replacing the current control loops with power control loops simplifies the system design and enhances the transient performance. The simulation models in MATLAB/Simulink and the digital signal processor-controlled 1.5 kW Vienna-type rectifier are used to verify the fast responses and robustness of the proposed control scheme.

• Journal of Power Electronics
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• v.18 no.6
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• pp.1791-1804
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• 2018

To achieve a fast dynamic response and to solve the multi-objective control problems of the output currents, capacitor voltages and system constraints, this paper proposes a deadbeat and hierarchical predictive control with space-vector modulation (DB-HPC-SVM) for five-level nested neutral point piloted (NNPP) converters. First, deadbeat control (DBC) is adopted to track the reference currents by calculating the deadbeat reference voltage vector (DB-RVV). After that, all of the candidate switching sequences that synthesize the DB-RVV are obtained by using the fast SVM principle. Furthermore, according to the redundancies of the switch combination and switching sequence, a hierarchical model predictive control (MPC) is presented to select the optimal switch combination (OSC) and optimal switching sequence (OSS). The proposed DB-HPC-SVM maintains the advantages of DBC and SVM, such as fast dynamic response, zero steady-state error and fixed switching frequency, and combines the characteristics of MPC, such as multi-objective control and simple inclusion of constraints. Finally, comparative simulation and experimental results of a five-level NNPP converter verify the correctness of the proposed DB-HPC-SVM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1052-1058
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• 2005

This paper dealt with the design and fabrication of a low frequency electronic ballast for ruh attracting lamps. The proposed electronic ballast was composed of a full-wave rectifier, a step don converter operated as a constant power controled current source, an inverter operated by 130 Hz square wave, and an ignition circuit. An acoustic resonance phenomenon of discharge lamps could be eliminated by application of 130 Hz square wave. Also, a circuit of high voltage pulse generation for lamp ignition was added to the ballast. From the experimental results, voltage and current of the lamp operated by the electronic ballast were estimated 132.5 V and 7.6 A, respectively. and the power consumption was about 1,000 W. The weight of the ballast, which is one of important advantages, was reduced to one-fifth of conventional magnetic ballasts.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.665-667
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• 2010

In this paper, the method to detect the IM(Inter Modulation) components of power amplifier is proposed by using frequency down-convertor. Output signals of power amplifier which is coupled by 20dB coupler and divided by power divider are applied to RF and LO of the frequency converter. It could be found the magnitude of IM components of power amplifier as a converted DC voltage which is come from the difference between 3th and 5th IM component. The detected DC voltage values are changed from 0.72V to 0.9V when 3rd IM component level changed from -26.4dBm to +2.15dBm and 5th IM component level changed from -34.2dBm to -12.89dBm as the Vgs of 3W power amplifier is changed.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.89-96
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• 2015

This paper presents a high efficiency, PSM/DCM/CCM triple mode boost DC-DC converter for mobile application. This device operates at Pulse-Skipping Mode(PSM) when it enters light load, and otherwise operate the operating frequency of 1.4MHz with Pulse-Width Modulation(PWM) mode. Especially in order to improve the efficiency during the Discontinuous-Conduction Mode(DCM) operation period, the reverse current prevention circuit and oscillations caused by the inductor and the parasitic capacitor to prevent the Ringing killer circuit is added. The input voltage of the boost converter ranges from 2.5V ~ 4.2V and it generates the output of 4.8V. The measurement results show that the boost converter provides a peak efficiency of 92% on CCM and 87% on DCM. And an efficiency-improving PWM operation raises the efficiency drop because of transition from PWM to PFM. The converter has been fabricated with a 0.18um Dongbu BCDMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.35-42
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• 2004

A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.1
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• pp.51-58
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• 2001

Recently, DC-DC converters significantly increase the total losses as rising switching frequency. Trnditional soft switching technique for reducing switching losses even increase voltage/Clment stress of switch In this paper, Resonant circuit for soft switching is connected in parallel with power stage and only operates just before tum-on of the main sWItch. Therefore, ills doesn't affect the total circuit QI'||'&'||'pound;ration. The object of tIns paper is to make the linearized equivalent loss mxleIs. and to analyze the total losses by experiment. ZVT-PWlvI converter designed with 170-260[V] input, 400[V] 5[A] output, and 100[kHz] switching frequency is tested respectively with 500[W], 1[kW], 1.5[kW], and 2[kW] loads. The total losses in input 220[V], 2[kW] load are analyzed by usirm the linearized equivalent loss models.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.