• Journal of Sensor Science and Technology
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• v.31 no.2
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• pp.115-119
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• 2022

A readout circuit for a mercury-cadmium-telluride (MCT)-amplified mid-wave infrared (IR) photodetector was realized and applied to noncontact chemical agent detectors based on a quantum cascade laser (QCL). The QCL emitted 250 times for each wavelength in 0.2-㎛ steps from 8 to 12 ㎛ with a frequency of 100 kHz and duty ratio of 10%. Because of the nonconstant QCL emission power during on-duty, averaging the photodetector signals is essential. Averaging can be performed in digital back-end processing through a high-speed analog-to-digital converter (ADC) or in analog front-end processing through an integrator circuit. In addition, it should be considered that the 250 IR data points should be completely transferred to a PC during each wavelength tuning period of the QCL. To average and minimize the IR data, we designed a readout circuit using the analog front-end processing method. The proposed readout circuit consisted of a switched-capacitor integrator, voltage level shifter, relatively low-speed analog-to-digital converter, and micro-control unit. We confirmed that the MCT photodetector signal according to the QCL source can be accurately read and transferred to the PC without omissions.

• Journal of IKEEE
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• v.13 no.4
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• pp.9-14
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• 2009

This paper describes measurement of an on-ship power supply noise in mixed-signal integrated circuits. To measure the on-chip power supply noise, we can check the effects of analog circuits and compensate it. This circuit consists of two independent measurement channels, each consisting of a sample and hold circuit and a frequency to digital converter which has a buffer and voltage controlled oscillator(VCO). The time-based voltage information and frequency-based power spectrum density(PSD) can be achieved by a simple analog to digital conversion scheme. The buffer works like a unit-gain buffer with a wide bandwidth and VCO has a high gain to improve resolution. This circuit was fabricated in a 0.18um CMOS technology and has 2.06mV/count. The noise measurement circuit consumes 15mW and occupies $0.768mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.4
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• pp.811-818
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• 2016

A continuous fine-tuning phase locked loop with an additional negative feedback loop has been proposed. When the phase locked loop is out-of-lock, the phase locked loop has a fast locking characteristic using the continuous band-selection loop. When the phase locked loop is near in-lock, the bandwidth is narrowed with the fine loop. The additional negative feedback loop consists of a voltage controlled oscillator, a frequency voltage converter and its internal loop filter. It serves a negative feedback function to the main phase locked loop, and improves the phase noise characteristics and the stability of the proposed phase locked loop. The additional negative feedback loop makes the continuous fine-tuning loop work stably without any voltage fluctuation in the loop filter. Measurement results of the fabricated phase locked loop in $0.18{\mu}m$ CMOS process show that the phase noise is -109.6dBc/Hz at 2MHz offset from 742.8MHz carrier frequency.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1884-1893
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• 2016

The ride-through control of a doubly-fed induction generator (DFIG) for the voltage sags on wind farms utilizing crowbar circuits by which the rotor side converter (RSC) is disabled has being reported in many literatures. An analysis and calculation of the transient current when the RSC is switched off are of significance for carrying out the low voltage ride through (LVRT) of a DFIG. The mathematical derivation is highlighted in this paper. The zero-state and zero-input responses of the transient current in the frequency domain through a Laplace transformation are investigated, and the transient components in the time domain are achieved. With the characteristics worked out from the linear resolving without modeling simplification, the selection of the resistance in the linear crowbar circuit and the value conversion from a linear circuit to a nonlinear one is proposed to setup the attenuation rate. In terms of grid code requirements, the theoretical analysis for the time constant of the transient components attenuation insures the controllability when the excitation of the RSC is resumed and it guarantees the reserved time for the response of the reactive power compensation. Simulations are executed in MATLAB/SIMPOWER and experiments are carried out to validate the theoretical analysis. They indicate that the calculation method is effective for selection of the resistance in a crowbar circuit for LVRT operations.

• Journal of the Korean Society for Railway
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• v.20 no.3
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• pp.329-338
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• 2017

A recent trend of technical development in auxiliary-power-supplies (APS) is to replace 60Hz low frequency transformers with isolated type dc/dc converters. This paper introduces the technical trend in APS structures and proposes a power converter circuit suitable for high-efficient and light-weight APS. By utilizing the resonant converter, which achieves ZCS, to reduce switching losses, various types of APS structures (1-stage and 2-stage) are reviewed, and they are verified by simulation. The full-bridge resonant LLC converter is designed with a 1-stage power converting structure; the resonant converter topology is designed with a 2-stage power converting structure that has a pre-regulator converter to compensate for the wide input voltage range. Both a step-down converter and a step-up converter are designed and compared for the pre-regulator in the 2-stage structure. Operational characteristics are compared with simulation results and loss analyses are presented to proposes appropriate system structure and topologies.

• Proceedings of the KIEE Conference
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• 2002.11d
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• pp.263-266
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• 2002

In this paper, It is indicating that an issues of the conventional boost converter for high frequency induction heating. To improve those issues, it is proposed, simulated and analyzed that the current resonant circuit, simulated. As the result, we knew that the proposed circuit has a good point to improve the waveform of input current and to make high efficiency. On the other side, in the inverter for the high current power supply, it is proposed that the high frequency inverter of the half bridge topology, be done the circuit analysis to extract the optimal circuit parameter. It is making sure of the soft switching operating by the inductor to reverse parallel connected on the inverter main switch, decreasing the surge voltage when the switch is turn-off by compulsion, and repressing the switch current and bringing the high current amplitude operation by the multi resonance.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.10
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• pp.587-594
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• 2002

A low frequency square wave electronic ballast for the high intensity discharge(HID) lamps using fuzzy logic controller is developed. This electronic ballast consists a buck converter, a low frequency square wave full bridge inverter, a high voltage pulse generator for the HID lamp ignition, an over current protection circuit and an 8-bit microcontroller. The ballast system is operated on the constant current mode during the HID lamp start-up process and the system is operated on the constant power mode during steady state. Experimental results show that the fuzzy logic control operation is carried out successfully by the 8-bit microcontroller PIC16F877 In this electronic ballast system, in spite of the limited control bandwidth caused by low operating speed of the microcontroller, the good performance in the constant lamp current characteristic is obtained. Acoustic resonance of the HID lamps can be effectively avoided because the instantaneous In lamp power is fully constant due to the low frequency square wave drive.

• Journal of Power Electronics
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• v.11 no.3
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• pp.271-278
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• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.312-320
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• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.