• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.921-930
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• 2016

This paper proposes a design and control method for a high-voltage direction current modular multilevel converter (HVDC-MMC) considering the capacitor voltage ripple of the submodule (SM). The capacitor voltage ripple consists of the line frequency and double-line-frequency components. The double line- frequency component does not fluctuate according to the active power, whereas the line-frequency component is highly influenced by the grid-side voltage and current. If the grid voltage drops, a conventional converter increases the current to maintain the active power. A grid voltage drops, current increment, or both occur with a capacitor voltage ripple higher than the limit value. In order to reliably control an MMC within a limit value, the SM capacitor should be designed on the basis of the capacitor voltage ripple. In this paper, the capacitor voltage ripple according to the grid voltage and current are analyzed, and the proposed control method includes a current limitation method considering the capacitor voltage ripple. The proposed design and control method are verified through simulation using PSCAD/EMTDC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.949-954
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• 2007

In this work, temperature stable frequency-to-voltage converter is proposed. In FVC circuit input frequency is converted into output voltage signal. A FLL is similar to PLL in the way that it generates an output signal which tracks an input reference signal. A PLL is built on a phase detector, a charge pump, and a low pass filter. However, FLL does not require the use of the phase detector, the charge pump and low pass filter. The FVC is designed by using $0.25{\mu}m$ CMOS process technology. From simulation results, the variation of output voltage is less than ${\pm}2%$ in the temperature range $0^{\circ}C\;to\;75^{\circ}C$ when the input frequency is from 70MHz to 140MHz.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.233-236
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• 2000

A new time-to-digital converter is designed and the converter is based on a voltage-to-frequency converter and a counter. The converter output is obtained without delay time and the resolution improves with increasing input time interval because the output of voltage-to-frequency converter increases linearly. In the designed circuit the input time intervals range is from 100nsec to 3${\mu}$ sec.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.12
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• pp.813-820
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• 2000

A technique to suppress the low frequency ripple voltage of the DC output in three phase buck diode converter is presented in this paper. The proposed pulse frequency modulation methods and duty ratio modulation methods are employed to regulate the output voltage of the buck diode converter and guarantee zero-current-switching(ZCS) of the switch over the wide load range. The proposed control methods used in this paper provide generally good performance such as low THD of the input line current and unity power factor. In addition, control methods can be effectively used to suppress the low frequency ripple voltage appeared in the dc output voltage. The harmonic injection technique illustrates its validity and effectiveness through the simulations and experiments.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.431-437
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• 2022

This study proposes a converter that makes battery charging, discharging, and zero voltage control possible. The proposed topology consists of an LLC converter and a half-bridge inverter, and all power semiconductor devices are applied Si-MOSFETs. The topology is designed with an LLC switching frequency of 100 kHz, a half-bridge inverter switching frequency of 50 kHz, and a battery voltage of 5 V. The advantages of the charging/discharging operation of the 5 V battery voltage and the zero voltage control of the battery are verified. In addition, by using a two-stage topology, the battery can be charged, discharged through current control, and discharged to zero voltage. With the proposed topology, the current can be maintained even when the battery voltage drops to zero.

• Journal of Electrical Engineering and Technology
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• v.1 no.2
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• pp.216-225
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• 2006

This paper presents a new circuit topology of DC busline switch and snubbing capacitor-assisted full-bridge soft-switching PWM inverter type DC-DC power converter with a high frequency link for low voltage large current applications as DC feeding systems, telecommunication power plants, automotive DC bus converters, plasma generator, electro plating plants, fuel cell interfaced power conditioner and arc welding power supplies. The proposed power converter circuit is based upon a voltage source-fed H type full-bridge high frequency PWM inverter with a high frequency transformer link. The conventional type high frequency inverter circuit is modified by adding a single power semiconductor switching device in series with DC rail and snubbing lossless capacitor in parallel with the inverter bridge legs. All the active power switches in the full-bridge inverter arms and DC busline can achieve ZVS/ZVT turn-off and ZCS turn-on commutation operation. Therefore, the total switching losses at turn-off and turn-on switching transitions of these power semiconductor devices can be reduced even in the high switching frequency bands ranging from 20 kHz to 100 kHz. The switching frequency of this DC-DC power converter using IGBT power modules is selected to be 60 kHz. It is proved experimentally by the power loss analysis that the more the switching frequency increases, the more the proposed DC-DC converter can achieve high performance, lighter in weight, lower power losses and miniaturization in size as compared to the conventional hard switching one. The principle of operation, operation modes, practical and inherent effectiveness of this novel DC-DC power converter topology is proved for a low voltage and large current DC-DC power supplies of arc welder applications in industry.

• Journal of information and communication convergence engineering
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• v.10 no.2
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• pp.187-193
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• 2012

A 1 GHz CMOS fast-lock phase-locked loop (PLL) is proposed to support the quick wake-up time of mobile consumer electronic devices. The proposed fast-lock PLL consists of a conventional charge-pump PLL, a frequency-to-digital converter (FDC) to measure the frequency of the input reference clock, and a digital-to-analog converter (DAC) to generate the initial control voltage of a voltage-controlled oscillator (VCO). The initial control voltage of the VCO is driven toward a reference voltage that is determined by the frequency of the input reference clock in the initial mode. For the speedy measurement of the frequency of the reference clock, an FDC with a parallel architecture is proposed, and its architecture is similar to that of a flash analog-to-digital converter. In addition, the frequency-to-voltage converter used in the FDC is designed simply by utilizing current integrators. The circuits for the proposed fast-lock scheme are disabled in the normal operation mode except in the initial mode to reduce the power consumption. The proposed PLL was fabricated by using a 0.18-${\mu}m$ 1-poly 6-metal complementary metal-oxide semiconductor (CMOS) process with a 1.8 V supply. This PLL multiplies the frequency of the reference clock by 10 and generates the four-phase clock. The simulation results show a reduction of up to 40% in the worstcase PLL lock time over the device operating conditions. The root-mean-square (rms) jitter of the proposed PLL was measured as 2.94 ps at 1 GHz. The area and power consumption of the implemented PLL are $400{\times}450{\mu}m^2$ and 6 mW, respectively.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.193-196
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• 2000

In this work, I propose a temperature stable voltage-to-frequency converter in which the output frequency is directly proportional to the input voltage. The output frequency range is from 20㎑ to 60㎑ and the difference between simulated and calculated values is less than about 5％ for this range of output frequency. The temperature variation of sample output frequencies is less than ${\pm}$0.5％ in the temperature range -25$^{\circ}C$ to 75$^{\circ}C$.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.537-538
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• 2008

A step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in 0.18um CMOS standard process. In an effort to improve low load efficiency, this paper proposes the PFM (Pulse Frequency modulation) voltage mode 1MHz switching frequency step-down DC-DC converter with on-chip compensation. Capacitor multiplier method can minimize error amplifier compensation block size by 20%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87% for the output voltage of 1.8V (input voltage : 3.3V), maximum load current 500mA, and 0.14% output ripple voltage. The total core chip area is $mm^2$.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.4
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• pp.384-394
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• 1999

This paper deals with a fixed frequency full-bridge inverter type DC-DC high-power converter with high frequency high voltage(HFHV) transformer-coupled stage, which operates under quasi-resonant ZVS transition priciple in spite of a wide PWM-based voltage regulation processing and largely-changed load conditions. This multi-resonant(MR) converter topology is composed of a series capacitor-connected parallel resonant tank which makes the most of parasitic circuit reactive components of HFHV transformer and two additional quasi-resonant pole circuits incorporated into the bridge legs. The soft-switching operation and practical efficacy of this new converter circuit using the latest IGBTs are actually ascertained through 50kV trially-produced converter system operating using 20kHz/30kHz high voltage(HV) transformers which is applied for driving the diagnostic HV X-ray tube load in medical equipments. It is proved from a practical point of view that the switching losses of IGBTs and their electrical dynamic stresses relating to EMI noise can be considerably reduced under a high frequency(HF) switching-based phase-shift PWM control process for a load setting requirements.