• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3117-3119
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• 1999

In this paper, a new phase detector which can detect phase difference of variable input frequency and represent as a DC voltage is designed. The proposed phase detector has detection range from $-180^{\circ}$ to $180^{\circ}$. It is implemented by digital electronic circuit. It operates from 125 kHz to 4 MHz frequency of input signal and it's maximum phase error is $360/256^{\circ}$.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.217-220
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• 2000

In this paper, A low-power MOS monolithic peak detector is presented. Designed for monolithic and low-power characteristics, this MOS peak detector can be integrated easily on the same chip as a module of large communication systems. The simulation results of this peak detector which was composed with four NMOSs and two capacitors show the power dissipation of 0.972㎽ and the good operations for 2㎓ operating pulse frequency. Therefore, it may be used as a functional block for various signal processing systems.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.201-204
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• 2000

In this paper, a new multiuser detector combining multicarrier and decorrelating detection schemes is proposed and analyzed in a frequency selective Rayleigh fading channel. The bit error probability is derived and compared with that of the conventional decorrelating detector. From the numerical results, it is shown that the proposed detector achieves better BER performance and lower computational complexity than those of the conventional decorrelating detector.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.447-448
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• 2008

This paper presents a low-complexity design and implementation results of a multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) symbol detector for high speed wireless LAN (WLAN) systems. The proposed spatial division multiplexing (SDM) symbol detector is designed by HDL and synthesized to gate-level circuits using 0.18um CMOS library. The total gate count for the symbol detector is 238K.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.10-15
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• 2006

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase and frequency detector structure without a reference clock is described. The phase detector (PD) and frequency detector (FD)are designed by 4X oversampling method. The PD, which uses bang-bang method, finds the phase error by generating four up/down signal and the FD, which uses the rotational method, finds the frequency error by generating up/down signal made by the PD output. And the six signals of the PD and the FD control an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the 0.18um CMOS technology and operating voltage is 1.8V. With a 4X oversampling PD and FD technique, tracking range of 24% at 3.125Gbps is achieved.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.13 no.6
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• pp.109-114
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• 2013

The biological active points (BAP) are known as low resistance spots or good electro-permeable points. In this paper, a new method for BAP detection using the bio-impedance measurement system based on the adaptive frequency tracking filter (AFTF) and the transition event detector is presented. Also, the microcontroller process continuous time demodulation of the modulated signal by multi frequency components using the AFTF. The transition event detector based on the phase space method is applied about each frequency using the BAP equivalent model which is proposed.

• Journal of IKEEE
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• v.17 no.3
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• pp.248-253
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• 2013

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

• Korean Journal of Optics and Photonics
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• v.22 no.5
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• pp.223-229
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• 2011

We present a low jitter frequency up-conversion detector based on quasi-phase matched sum frequency generation in a periodically poled $LiNbO_3$ waveguide for efficient single-photon detection at 1.5 ${\mu}m$ telecommunication wavelengths. The maximum detection efficiency and the noise count rate using the pump power of 300 mW and the pump wavelength of 974 nm are about 7% and 480 kHz, respectively. We also characterize the timing jitter of the frequency up-conversion detector by analyzing the time distribution of the detection outputs for photons generated through a picosecond pump pulsed spontaneous parametric downconversion. The minimum timing jitter was measured to be about 39.1 ps. Coincidence measurement with a narrow time window for pulsed up-conversion photons can eliminate the unwanted noise counts and maximize signal to noise ratio.

• Nuclear Engineering and Technology
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• v.56 no.4
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• pp.1532-1537
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• 2024

Time-of-flight (TOF) PET detectors with fast-rise-time scintillators and fast-single photon time resolution silicon photomultiplier (SiPM) have been developed to improve the coincidence timing resolution (CTR) to sub-100 ps. The CTR can be further improved with an optimal bandwidth and minimized electronic noise in the readout circuit and this helps reduce the distortion of the fast signals generated from the TOF-PET detector. The purpose of this study was to develop an ultra-high frequency and fully-differential (UF-FD) readout circuit that minimizes distortion in the fast signals produced using TOF-PET detectors, and suppresses the impact of the electronic noise generated from the detector and front-end readout circuits. The proposed UF-FD readout circuit is composed of two differential amplifiers (time) and a current feedback operational amplifier (energy). The ultra-high frequency differential (7 GHz) amplifiers can reduce the common ground noise in the fully-differential mode and minimize the distortion in the fast signal. The CTR and energy resolution were measured to evaluate the performance of the UF-FD readout circuit. These results were compared with those obtained from a high-frequency and single ended readout circuit. The experiment results indicated that the UF-FD readout circuit proposed in this study could substantially improve the best achievable CTR of TOF-PET detectors.