• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.333-341
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• 2015

In this paper, a 0.5~4 GHz frequency synthesizer having good phase noise performance is proposed. Wideband output frequencies of the synthesizer were synthesized using DDS(Direct Digital Synthesizer) and analog direct frequency synthesis technology in order to obtain fast settling time. Also in order to get good phase noise performance, 2.4 GHz DDS clock was generated by VCO(Voltage Controlled Oscillator) which was locked by the 100 MHz reference oscillator using SPD(Sample Phase Detector). The phase noise performance of wideband frequency synthesizer was estimated and the results were compared with the measured ones. The measured phase noise of the frequency synthesizer was less then -121 dBc @ 100 kHz at 4 GHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Journal of Magnetics
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• v.15 no.4
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• pp.213-220
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• 2010

Since the hypothalamus immediately reacts to a nerve by processing all the information from the human body and the external stimulus being conducted, it performs a significant role in internal secretion; thus, a diverse and rapid stimulus pulse is required. By detecting Zero Detector accurately via the application of AVR on-Chip (ATMEL) using commercial electricity, chopping generates a stimulus pulse to the brain using an IGBT gate to designate a new magnetic stimulation following treatment and diagnosis. To simplify and generate a diverse range of stimuli for the brain, chopping can be used as a free magnetic stimulator. Then, commercial frequency (60Hz) is chopped precisely at the first level of the leakage transformer to deliver an appropriate stimulus pulse towards the hypothalamus when necessary. Discharge becomes stable, and the chopping frequency and duty-ratio provide variety after authorizing a high-pressure chopping voltage at the second level of the magnetic stimulator. These methods have several aims. The first is to apply a variable stimulus pulse via accurate switching frequency control by a voltaic pulse or a pulse repetition rate, according to the diagnostic purpose for a given hypothalamus. Consequently, the efficiency tends to increase. This experiment was conducted at a maximum of 210 W, a magnetic induced amplitude of 0.1~2.5 Tesla, a pulse duration of $200{\sim}350\;{\mu}s$, magnetic inducement of 5 Hz, stimulus frequency of 0.1~60 Hz, and a duration of stimulus train of 1~10 sec.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.19-25
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• 2001

In this paper, the design and simulation results of IF frequency synthesizer section has been described. We has been used 0.8 $\mu\textrm{m}$ BiCMOS device and library of the AMS. IF frequency synthesizer section has been contained IF VCO, Phase Detector, Divide_by_8, Charge Pump and Loop Filter. IF frequency synthesizer has been shown operating voltage of 2.7~3.6 V, control voltage of 0.5~2.7 V and supply current of 11 mA. The measured results have been showed good agreement with the simulation results about supply current.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.74-81
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• 2004

We propose a novel scheme to transmit high center frequency RF signals using electroabsorption devices (EADs) as frequency converters at the transmitter and the receiver. In this approach frequency heterodyning is employed for obtaining high center frequency. With the EAD as a detector/mixer at the receiver we demonstrated a smaller conversion loss than that of the conventional modulator/mixer. With EAD as a modulator/mixer at the transmitter and with two heterodyned lasers to generate an optical local oscillator (LO), we demonstrated a large reduction (${\sim}23dB$) in conversion loss, and the transmission is not limited by the optical saturation of the EAD. This transmission scheme has optical single-side-band transmission feature which greatly relieves the fiber dispersion effect.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.307-307
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• 2004

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.342-348
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• 2015

This paper presents a new motion detector that has a bubble-layer detection zone using a pulsed-mode oscillator and delay line. The proposed motion detector controls the bubble-layer detection zone with pulse width of transmitted signals and creates IF signals only by reflected signals from the target within the detection zone whose position is determined by time delay of the delay line. The fabricated motion detector uses the pulsed-mode voltage controlled oscillator as a signal source which has a center frequency of 8 GHz, pulse width of 2 nsec and pulse period of 30 nsec. It successfully makes the bubble-layer detection zones at 1 m, 3 m and 5 m distant from itself using two delay lines with 7 nsec and 12 nsec delay, and is also demonstrated to detect the target within the detection zones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.7
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• pp.1645-1652
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• 2013

In this paper, a new piezoelectric transducer for high performance ultrasonic flaw detector used in non-destructive test (NDT) is implemented. Here, the goals for some major characteristics such as piezoelectric strain constant and electro-mechanical coupling factor are fixed in advanced. Then, the parameters obtained by finite element analysis (FEA) are exploited to design and implement the piezoelectric transducer. As a result of experiments using manufactured samples, it is proved that the new PZT ceramics satisfy the goals very well. It has much improved impedance characteristic at the resonant frequency and generation of ultrasonic signals. In addition, ultrasonic flaw detector with the new transducer provides increased flaw detecting gain than the conventional one. Thus, it is considered that the new flaw detector contributes significantly to improve reliability of the NDT.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.10
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• pp.1147-1158
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• 2008

In this paper, we designed a phase-looking circuit that locks the 16.8 GHz VTDRO to a 700 MHz SAW oscillator using SPD as a phase detector Direct phase locking with loop filter alone causes the problem of lock time, so VTDRO is phase leered by loop filter with the aid of time varying square wave current generator. The current generator is related to the loop filter and needs the systematic toning. In this paper, a systematic design of the current generator and loop filter is presented. The fabricated PLDRO shows a stabilized frequency of 16.8 GHz, a output power 6.3 dBm, and a phase noise of -101 dBc/Hz at the 100 kHz offset.