• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1088-1097
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• 1999

In this paper we describe our investigation en ATM CLR(Cell Loss Rate) in the wireless ATM Networks, which consist of wireless access nodes and wireless links. A wireless access node is modelled as the ND/D/1queue. A wireless channel is modelled as channel with single and burst error characteristics, and it can be seen that the CLR degrades on a link with burst errors than on a link with single error. Because wireless channel can be approximated as the Rayleigh or Rician fading channel and wireless communication systems are power limited, it is customary that the CLR degrades on a link with burst errors than on a link with single error. So error control method should be used to improve performance degradation caused by burst errors. We consider the forward error correction(FEC) as error control scheme for CBR traffics to improve performance degradation caused by burst errors, and analyze performance of concatenated FEC scheme through the use of CLR.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.07a
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• pp.212-212
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• 2004

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.140-148
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• 2013

This paper presents a iterative Bose-Chaudhuri-hocquenghem (i-BCH) code and its high-speed decoder architecture for 100 Gb/s optical communications. The proposed architecture features a very high data processing rate as well as excellent error correction capability. The proposed 6-iteration i-BCH code structure with interleaving method allows the decoder to achieve 9.34 dB net coding gain performance at $10^{-15}$ decoder output bit error rate to compensate for serious transmission quality degradation. The proposed high-speed i-BCH decoder architecture is synthesized using a 90-nm CMOS technology. It can operate at a clock frequency of 430 MHz and achieve a data processing rate of 100 Gb/s. Thus, it has potential applications in next generation forward error correction (FEC) schemes for 100 Gb/s optical communications.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2000.11b
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• pp.15-19
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• 2000

This paper is about MPEG-4 error resilience tools of video streaming on packet service(ex, Internet). It is need to packetization for MPEG-4 video transport by packet unit on MPEG-4 system, this paper suggest packetization method of minimizing packet error on packet service[1]. FEC(Forward Error Correction) and retransmission is usually used for recovery of packet loss, and this paper suggest applying these method to DMIF(Delivery Multimedia Integration Framework) for minimizing packet loss[2].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.10
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• pp.2687-2702
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• 1996

It is desirable that the implementation of next generation information infrastructure is the Integrated Network combining the satellite and the terrestrial network. The application of the ATM network being the dominant infrastrure of terrestrial network to the satellite network is being studied variously. Considering these concepts, this paper analyzes due to ATM transport via satellite, evaluates the degradation of QoS and proposes reliable method of ATM cell transport via satellite. Because ATM is investigated with the optical fiber which is almost error free characteristics, the practical application of ATM transport via satellite essentially need the channel coding(FEC:Forward Error Correction) to enhance BER performance. But using the FEC coding, satellite link has burst error characteristics which evoke severe performance degradation fo ATM QoS. Therefore in satellite link, we analyze burst error characteristics using experimental results of computer simulation. Then to compensate these characteristics, based on this analysis and HEC dual mode algorithm we propose various interleaver structures(Block interleaver, Intra interlever, and Inter-Intra interleaver) to improve cell transmission QoS. We execute performance evaluations of iterleaver structures by computer simulation.

• Journal of Broadcast Engineering
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• v.5 no.2
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• pp.227-238
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• 2000

This paper, at first, provides analysis on loss pattern of Internet based on real experiments of the current Internet. Then, we propose an effective adaptive QoS management technique, in which measured loss pattern as well as PLR (Packet Loss Ratio) are used to select titrate of temporal scalability. level of FEC and retransmission This selection is also incorporated to the MPEG-4 error resilience tools and error concealment techniques. In order to minimize effect of packet loss, multimedia stream is segmented in the unit of group of Pictures (GOP) and interleaving and FEC are applied to the segment. Proposed algorithms are applied to build a VOD system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.6
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• pp.535-544
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• 1988

In this paper, the hybrid ARQ scheme, which is incorporated the selective-repeat ARQ system with the finite receiver buffer and the single-error-correcting and double-error-detecting(63.56) cyclic Hamming code system, has been investigated. As a result of simulation, the proposed hybrid ARQ scheme shows that that throughput efficiencies are improved by one error correction, and that the reversed codewords due to retransmission are delivered to the user in order by means of detecting two errors. The hybrid ARQ scheme significantly outperforms the FEC or the ideal selective-repeat ARQ system in the respect of throughput and reliability, especially when the channel error rate is approximately in the range from $10^{-2}$~$10^{-3}$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8A
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• pp.1348-1357
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• 2001

본 논문에서는 DAB 시스템에서 사용하는 FEC(Forward Error Correction) 블록을 하드웨어 크기를 고려하여 효율적인 구조를 갖도록 설계하였다. DAB 시스템의 FEC 블록은 크게 스크램블러(에너지분산), 리드-솔로몬 코더, 길쌈 인터리버로 구성된다. RS 디코더 블록 중 키 방정식을 계산해 내는 블록과 길쌈 인터리버가 차지하는 하드웨어 비중은 굉장히 크다. 본 논문에서는 스크램블러 부분에서 데이터의 시작을 알려주는 신호의 효율적인 검출기법을 제안하고, 리드-솔로몬 디코더 블록의 수정 유클리드 알고리즘을 효율적인 하드웨어로 구현하기 위한 새로운 구조와 길쌈 인터리버에서 최적의 메모리 구조를 효과적인 구조를 제안한다. 제안한 구조에서는 단지 8개의 GF 곱셈기와 4개의 덧셈기만을 가지고 RS 디코더의 수정 유클리드 알고리즘을 구현하였으며, 2 RAM(128)과 4 RAM(256)을 가지고 컨벌루셔널 인터리버를 구현하였다. 제안한 구조로 설계했을 경우 디코더 블록이 Altera-FPGA 칩(FLEX10K)에 모두 들어갈 수 있었다.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06d
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• pp.250-252
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• 2006

ALC(Asyncronous Layered Coding)는 LCT(Layered Coding Transport)기반의 폭넓은 확장성과 다양한 전송속도로 신뢰성 있는 멀티캐스트 전송을 주 목적으로 한다. ALC는 다른 RMT 프로토콜과는 달리 재전송을 하지 않고 receiver-driven 형태의 혼잡제어를 하기 때문에 신뢰성을 제공하기 위해 FEC(Forward Error Correction) 스킴를 이용한다. 본 논문은 신뢰적인 멀티캐스트 전송 프로토콜을 위해 ALC와 FEC 스킴 중 하나인 LDPC 코드를 이용하여 구현한다. 인코딩 비율(Encoding ratio)에 따라 일정 수준 이상의 복구 성공 확율에 대해 최대 허용 가능한 패킷 손실률을 측정하여 신뢰치를 측정한다. 마지막으로 일대다의 파일 전송 시, TCP와 비교하여 본 구현물의 유연성과 효율성에 대해 분석 및 평가한다.