• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.1027-1030
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• 2015

하드웨어 디자인 설계에서 초기 단계의 설계 오류 발견은 개발 비용 감소 및 설계 시간 단축 측면에서 그 효과가 매우 크다. 이러한 초기 설계 오류 발견을 위한 대표적인 방법으로는 정형 검증(formal verification)이 있으며, Cadence SMV(Symbolic Model Verifier)는 정형 검증을 위해 Verilog HDL(Hardware Description Language)을 SMV로 자동 변환 해주는 장점이 있지만, 사건 기반 구조(event based structures)의 sensitivity list에 대한 지원을 하지 않는 한계가 있다. 이에 본 논문에서는 Cadence SMV에서 디지털회로(digital circuit) 중 하나인 조합 논리회로(combinational logic circuit)를 sensitivity list가 고려된 검증이 가능하도록 하는 방법을 제안한다. 신뢰성 있는 실험을 위해 본 논문에서는 제안하는 방법의 일반적인 규칙을 도출하였고, 도출된 규칙이 적용된 SMV 파일을 생성하는 자동화 프로그램을 구현하여 실험하였다. 실험결과 제안한 방법을 적용한 경우 기존 Cadence SMV가 발견하지 못한 설계상의 오류를 발견할 수 있었다.

• Journal of the Korean Society for Railway
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• v.10 no.3 s.40
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• pp.365-371
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• 2007

The communication protocol for interface among railway signalling systems is designed and established as national standard in Korean from a few years ago. So the communication link for information transmission among railway signalling system can be a good example of application of this standard. Communication protocol which is standardized among Korean railway signalling is considered to apply information transmission. And we confirmed there is no the states of deadlock of livelock in std. protocol which is applied formal verification which is one of the analytic method for inspection of safety characteristics in the design course of protocol. But the safety of protocol has to necessarily accomplish this normal analysis approach about satisfying requirement matters with such this analytic approach. In this paper we analyzed the safety characteristics of standard protocol for Korean Railway signalling through the requirement matters for safety transmission of railway transmission system which is required in international standard. So through this study we confirm whether it satisfies safety requirement matters of the level which require in international standard and tried to confirm whether standard protocol has enough safety character in the real railway field.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.570-592
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• 2019

The Event-B design pattern is an excellent way to quickly develop a formal model of the system. Researchers have proposed a number of Event-B design patterns, but they all lack formal behavior semantics. This makes the analysis, verification, and simulation of the behavior of the Event-B model very difficult, especially for the control-intensive systems. In this paper, we propose a novel method to transform the Event-B synchronous control flow design pattern into the labeled transition system (LTS) behavior model. Then we map the design pattern instantiation process of Event-B to the instantiation process of LTS model and get the LTS behavior semantic model of Event-B model of a multi-level complex control system. Finally, we verify the linear temporal logic behavior properties of the LTS model. The experimental results show that the analysis and simulation of system behavior become easier and the verification of the behavior properties of the system become convenient after the Event-B model is converted to the LTS model.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.1
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• pp.64-88
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• 2024

Security and reliability are the utmost importance facts in intelligent networked vehicles. Stochastic Petri Net and Z (SPZN) as an excellent formal verification tool for modeling concurrent systems, can effectively handles concurrent operations within a system, establishes relationships among components, and conducts verification and reasoning to ensure the system's safety and reliability in practical applications. However, the application of a system with numerous nodes to Petri Net often leads to the issue of state explosion. To tackle these challenges, a refinement and abstraction method based on SPZN is proposed in this paper. This approach can not only refine and abstract the Stochastic Petri Net but also establish a corresponding relationship with the Z language. In determining the implementation rate of transitions in Stochastic Petri Net, we employ the interval average and weighted average method, which significantly reduces the time and space complexity compared to alternative techniques and is suitable for expert systems at various levels. This reduction facilitates subsequent comprehensive system analysis and module analysis. Furthermore, by analyzing the properties of Markov Chain isomorphism in the case study, recommendations for minimizing system risks in the application of intelligent parking within the intelligent networked vehicle system can be put forward.

• The Journal of the Korea Contents Association
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• v.6 no.11
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• pp.202-216
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• 2006

A number of process algebras are not well suitable for real-time navigation/delivery systems due to the following reasons: 1) lack of representation of process distributivity over some geographical space and 2) the indistinction of representation of process mobility from process distributivity over the space. To make the process algebra suitable to the systems, it seems to be necessary to separate the space representation from the mobility representation. This paper presents a formal method for this purpose, namely, Calculus of Abstract Real-Time Distribution, Mobility, and Interaction (CARDMI). For analysis and verification of behavioral properties, CARDMI defines a set of the spatial, temporal and the interactive deduction rules and a set of equivalence relations. The rules and equivalences can be abstracted hierarchically due to the spatial abstraction, too. CARDMI can be applied to virtual navigation/delivery system for contents, too.

• KIISE Transactions on Computing Practices
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• v.21 no.9
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• pp.604-609
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• 2015

The use of Operating System(OS) virtualization is increasing as it provides many useful features such as efficient use of hardware(HW), easy system migration, and isolation between virtual spaces which prevents errors effecting each other. Recent development in HW has made it possible to use OS virtualization in embedded systems. However, implementing OS virtualization means that a multiple number of schedulers are layered in a system, rendering it difficult to analyze the schedulability of the system and errors are easily produced. Errors in safety critical embedded systems can cause serious damage to life and property; thus, the hierarchical schedulability must be verified. In this paper, we propose a framework which supports formal modeling and verification of hierarchical scheduling systems with UPPAAL.

• Proceedings of the KSR Conference
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• 2004.10a
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• pp.1241-1246
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• 2004

The verification confirms a correspondence between requirements and a specification before implementing. The problem in the formal method verifying a protocol specification using model checking is that the protocol behaviors must be always specified in L TS(Label Transition System). But if Region Automata is applied to the model checking, it is enable to verify whether properties are true on specification specified in I/O FSM(Input/Output Finite State Machine) as well as LTS. In this paper, we verify the correctness of rail signal control protocol type 1 specified in I/O FSM by using model checking method and region automata. This removes many errors and ambiguities of an informal method used in the past and saves down expenditures and times required in the protocol development. Therefore it is expected that there will be an increase in safety, reliability and efficiency in terms of the maintenance of the signaling system by using the proposed verification methods.

• Nuclear Engineering and Technology
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• v.28 no.6
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• pp.594-601
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• 1996

To assure quality of safety critical software, software should be developed in accordance with software development procedures and rigorous software verification and validation should be performed. Software verification is the formal act of reviewing, testing or checking, and documenting whether software components comply with the specified requirements for a particular stage of the development phase [1]. New software verification methodology was developed and was applied to the Shutdown System No. 1 and 2(SDS1,2) for Wolsong 2, 3 and 4 nuclear power plants by Korea Atomic Energy Research Institute(KAERI) and Atomic Energy of Canada Limited(AECL) in order to satisfy new regulation requirements of Atomic Energy Control Board(AECB). Software verification methodology applied to SDS1 for Wolsong 2, 3 and 4 project will be described in this paper. Some errors were found by this methodology during the software development for SDS1 and were corrected by software designer. Output from Wolsong 2, 3 and 4 project have demonstrated that the use of this methodology results in a high quality, cost-effective product.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.3
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• pp.1-17
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• 2002

In this paper, we present our experiences in using symbolic model checker(SMV) to analyze a number of properties of RACE cache coherence protocol designed by ETRI(Electronics and Communications Research Institute) and to verify that RACE protocol satisfies important requirements. To investigate this, we specified the model of the RACE protocol as the input language of SMV and specified properties as a formula in temporal logic CTL. We successfully used the symbolic model checker to analyze a number of properties of RACE protocol. We verified that abnormal state/input combinations was not occurred and every possible request of processors was executed correctly We verified that RACE protocol satisfies liveness, safety and the property that any abnormal state/input combination was never occurred. Besides, We found some ambiguities of the specification and a case of starvation that the protocol designers could not expect before. By this verification experience, we show advantages of model checking method. And, we propose a new method to generate automatically test cases which are used in simulation and testing.

• Journal of Korea Multimedia Society
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• v.8 no.8
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• pp.1119-1133
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• 2005

As a very important part in development of the protocol, verification and conformance test for protocol specification are complementary techniques that are used to increase the level of confidence in the system functions as prescribed by their specifications. In this paper, we verify the safety and liveness properties of rail signal control protocol type 1 specified in LTS with model checking method, and experimentally prove that it is possible to check for the deadlock, livelock and rechability of the states and actions on LTS. The implemented formal checker is able to verify whether properties expressed in modal logic are true in specifications using modal mu-calculus. We also propose a formal method on generation of conformance test cases using the concept of UIO sequences from verified protocol specification. The suggested tools are implemented by C++ language under Windows NT.