Journal of the Institute of Electronics Engineers of Korea CI (전자공학회논문지CI)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Formal Verification and Testing of RACE Protocol Using SMV

SMV를 이용한 RACE 프로토콜의 정형 검증 및 테스팅

  • Published : 2002.05.01
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Abstract

In this paper, we present our experiences in using symbolic model checker(SMV) to analyze a number of properties of RACE cache coherence protocol designed by ETRI(Electronics and Communications Research Institute) and to verify that RACE protocol satisfies important requirements. To investigate this, we specified the model of the RACE protocol as the input language of SMV and specified properties as a formula in temporal logic CTL. We successfully used the symbolic model checker to analyze a number of properties of RACE protocol. We verified that abnormal state/input combinations was not occurred and every possible request of processors was executed correctly We verified that RACE protocol satisfies liveness, safety and the property that any abnormal state/input combination was never occurred. Besides, We found some ambiguities of the specification and a case of starvation that the protocol designers could not expect before. By this verification experience, we show advantages of model checking method. And, we propose a new method to generate automatically test cases which are used in simulation and testing.

본 논문은 심볼릭 모델 체커 SMV(Symbolic Model Verifier)를 이용하여, 한국전자통신연구원 (Electronics and Communications Research Institute)에서 개발한 캐쉬 일관성 프로토콜인 RACE(Remote Access Cache coherency Enforcement) 프로토콜의 몇 가지 특성(property)들을 검증함으로써, RACE 프로토콜이 중요 요구사항(requirement)들을 만족함을 보인다. 본 검증에서는 RACE 프로토콜의 모델을 SMV 입력 언어로 명세하며, 검증할 특성들을 CTL(Computational Tree Logic)을 이용하여 나타낸다. 본 검증을 통해서 RACE 프로토콜은 4개의 노드로 구성된 시스템에서 비정상적인 state/input 조합이 발생하지 않으며, liveness와 safety를 만족한다는 것을 검증하였다. 또한, 프로토콜 개발자들이 예상하지 못한 명세서 상의 모호성(ambiguity) 및 기아현상(starvation)을 발견하였으며, 본 검증 사례를 통하여 모델 체킹 기법이 하드웨어 프로토콜 검증에 효과적으로 이용될 수 있다는 것을 제안한다. 그리고, 검증시에 구현된 모델을 이용하여 시뮬레이션 및 테스팅에 유용하게 사용될 수 있는 테스트 케이스를 자동적으로 생성할 수 있는 새로운 방법을 제안한다.

Keywords

References

  1. David L. Dill and John Rushbv, Acceptance of Formal Methods: Lessons from Hardware Design, IEEE Computer, Vol. 29, No. 4, pp. 16-30, April 1996
  2. Vaughan Pratt, Anatomy of the Pentium Bug. In TAPSOFT 95: Theory and Practice of Software Development, Vol. 915 of Lecture Notes in computer Science, pp. 97-107, May 1995 https://doi.org/10.1007/3-540-59293-8_189
  3. G.J. Myers, The Art of Software Testing, Wiley, 1979
  4. K.L. McMillan and J.C. Schwalbe, Formal Verification of the Gigamax Cache Consistency Protocol, Proceedings of the ISSM International Conference on Parallel and Distributed Computing, Oct. 1991
  5. David Lee and Mihalis Yannalkakis, Principles and Methods of Testing Finite State Machines-A Survey, Proceedings of the IEEE, vol. 84, pp. 1090-1123, August 1996 https://doi.org/10.1109/5.533956
  6. R.K.Brayton et al. VIS: A System for Verification and Synthesis. In T.Henzinger and R.Alur, editors, 8th Conference on Computer Aided Verification, pp. 428-432, Springer-Verlag, 1996. LNCS 1102 https://doi.org/10.1007/3-540-61474-5_95
  7. Computer System Department of ETRI-CSTL RACE Protocol: Remote Access Cache coherency Enforcement Protocol, V1.1 Draft.TM-3100-1999-012, August 1999
  8. Computer System Department of ETRI-CSTL RACE Protocol: Remote Access Cache coherency Enforcement Protocol, V0.3 Draft, January 1999
  9. E.M. Clarke and E.A. Emerson, Synthesis of Synchronization skeletons for Branching Time Temporal Logic. Logic of Programs: Workshop, Vol. 131 of Lecture Notes in Computer Science, May 1981 https://doi.org/10.1007/BFb0025774
  10. Kenneth L. MaMillan, Symbolic Model Checking. Kluwer Academic Publishers, 1993
  11. R.E. Bryant, Graph-based Algorithms for Boolean Function Manipulationv, IEEE Transactions on Computers, Vol. 35, No. 6, pp. 677-691, August 1986 https://doi.org/10.1109/TC.1986.1676819
  12. F. Pong, A. Nowatzyk, G. Aybay and M. Dubois, Verifying Distributed Directory-based Cache Coherence Protocols: S3.mp a Case Study. Proceedings of the First International EURO-PAR Conference. pp. 287-300, August 1995
  13. Jean-Loup Baer and Wen-Hann Wnag, Architectural Choices for Multilevel Cache Hierarchies. Proceedings of the 1st International Conference on Parallel Processing, pp. 258-261, August 1987
  14. J.R. Burch, E.M. Clarke, and D.E. Long, Symbolic Model Checking with Partitioned Transition Relations, Proceedings of the 1991 Internaitonal Conference on VLSI, pp. 49-58, August 1991
  15. E.M. Clarke and J.M. Wing. Formal methods: State of the Art and Future Directions. ACM Computing Surveys, 28(4), pp. 626-643, December 1996 https://doi.org/10.1145/242223.242257
  16. E. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D. Long, K. McMillan, and L. Ness, Verification of the Futurebus+ cache coherence protocol, Formal Methods in System Design, 6(2), pp. 217-232, March 1995 https://doi.org/10.1007/BF01383968
  17. David L. Dill, Andreas J. Drexler, Alan J. Hu, and C. Han Yang, Protocol Verification as a Hardware Design Aid. IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 522-525, 1992 https://doi.org/10.1109/ICCD.1992.276232
  18. Ulrich Stern and David L. Dill, Automatic Verification of the SCI Cache Coherence Protocol, Correct Hardware Design and Verification Methods: IFIP WG10.5 Advanced Research Working Conference Proceedings, 1995
  19. J.R. Burch, E.M. Clarke, D.E. Long, K.L. McMillan, and D.L. Dill. Symbolic Model Checking for Sequential Circuit Verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 13(4):401-424 https://doi.org/10.1109/43.275352
  20. Paul Sweazey and Alan Jay Smith, A Class of Compatible Cache Consistency Protocols and Their Support by the IEEE Futurebus. Proceedings of the 13th Annual International Symposium on Computer Architecture, pp. 414-423, 1986 https://doi.org/10.1145/17407.17404
  21. G. Gonenc, A Method for the Design of Fault Detection Experiments. IEEE Transactions on Computing, vol. C-19, pp. 551-558, June 1970 https://doi.org/10.1109/T-C.1970.222975
  22. Deepinder P. Sidhu and Ting-Kau Leung, Formal Methods for Protocol Testing: A Detailed Study, IEEE Transactions on Software Engineering, 15(4), pp. 413-426 April 1989 https://doi.org/10.1109/32.16602
  23. S. Naito and M. Tsunoyama, Fault Detection for Sequential Machines by Transition Tours, Proceedings of IEEE Fault Tolerant Computing Conference, pp. 238-243, 1981
  24. K. Sabnani and A. Dahbura, A Protocol Test Generation Procedurev. Computer Networks ISDN System, vol. 15, pp. 285-297, 1988 https://doi.org/10.1016/0169-7552(88)90064-5