• The Transactions of the Korea Information Processing Society
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• v.5 no.4
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• pp.995-1004
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• 1998

This paper presents an implementation of model checking tool for LTS process specification, which checks deadlock, livelock and reachability for the state and action. The implemented formal checker using modal mu-calculus is able to verify whether properties expressed in modal logic are true on specifications. We prove experimentally that it is powerful to check, safety and liveness for the state and action on LTS. The tool is implemented by $C^{++}$ language and runs on IBM PC under Windows NT.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.3
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• pp.1-17
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• 2002

In this paper, we present our experiences in using symbolic model checker(SMV) to analyze a number of properties of RACE cache coherence protocol designed by ETRI(Electronics and Communications Research Institute) and to verify that RACE protocol satisfies important requirements. To investigate this, we specified the model of the RACE protocol as the input language of SMV and specified properties as a formula in temporal logic CTL. We successfully used the symbolic model checker to analyze a number of properties of RACE protocol. We verified that abnormal state/input combinations was not occurred and every possible request of processors was executed correctly We verified that RACE protocol satisfies liveness, safety and the property that any abnormal state/input combination was never occurred. Besides, We found some ambiguities of the specification and a case of starvation that the protocol designers could not expect before. By this verification experience, we show advantages of model checking method. And, we propose a new method to generate automatically test cases which are used in simulation and testing.

• Proceedings of the Korea Society for Simulation Conference
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• 1994.10a
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• pp.7-8
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• 1994

최근 들어 원자재, 재공품 또는 완제품을 신속하고 정확하게 공급/배분하기 위해 저장과 인출을 담당하는 Material Handling System을 이용하여 작업자의 개입요소를 줄이며, 제고관리 Computer를 이용하여 입고/출고 명령을 유효적절하게 처리하는 ASRS(Atomated Storage and Retreival System : 자동창고 시스템)가 널리 공급되고 있다. 중앙은행의 현금창고, 병원의 약품창고, 식품/화장품 회사의 배송창고, 군수물자의 군납창고에 이르기까지 물품의 저장 또는 공급의 필용성을 갖는 곳에서는 어디든지 찾아볼 수 있는 ASRS는 가깝게는 관공소나 대형빌딩의 주차장에도 이의 개념이 도입되어 사용됨을 볼 수 있다. 최근의 인금인상, 구인난등의 이유로 ASRS설치는 계속 증가할 추세에 있으나 자동 창고 시스템을 설치하기 위해서는 막대한 초기 투자가 필요하며 시스템의 설계 및 설치후 운영에 대한 연구가 반드시 필요하다. ASRS의 운영 Rule 검증, 수행능력 분석등의 목적을 갖는 연구에는 여러 접근방법이 있을 수 있으나 구성 설비와 운영 Rule의 복잡한 관계로 컴퓨터 시뮬레이션의 거의 유일한 문제해결 방법이다. ASRS의 Modeling에 관한 기존의 연구로는 수리모델 수립. 이산사건 시스템의 관점에서 event-graphy, petri-net을 이용한 modeling이 있으며 ASRS에 대한 전용 Simulator 개발등이 진행되었다. 본 연구의 대상 시스템은 2개의 Rack과 하나의 Stacker Crane 으로 구성된 Aisle과 입출고의 물류를 처리하는 순환 RGVS(Rail Guided Vehicle System), 입/출고장을 구성하는 Conveyor Net등으로 이루어진 제조-물류시스템의 일반적인 ASRS이다. 또 이 ASRS의 입/출고 방식은 전수 입/출고만을 포함하며 Blocking 방지를 위한 Capaicty 예약, 다중설비 선택등의 문제등을 고려하고 있다. 본 연구의 접근방법으로는 ASRS의 개념적인 Reference Model을 수립하고 이 Reference Model에 대한 Formal Model로 DEVS(Discrete Event System Specification)을 이용하여 시스템을 Modeling하였다. 이의 Computer Simulation을 위하여 DEVS형식론 환경에서의 Simulation Language인 DEVSim ++ⓒ를 이용하여 시스템을 구현하였다.

• Archives of design research
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• v.17 no.3
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• pp.335-342
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• 2004

Recently there have been various research activities regarding Korean traditional aesthetics. However, those researches were mainly conducted individually, partially, and periodically, which resulted in unsystematic and incomprehensive works. Therefore, it is required to orginze all the precedent research works with more systematic and objective framework. Generally speaking, all the human activities including aesthetic activity have ends, procedure and means. In other words, human being needs three key elements for realizing any thought and those three elements include contents, formal, and practical element. Element of contents is ultimate goal to accomplish as value, concept, and meaning of thought with their aims. Formal element includes methods, principles, norms, procedure, formality and style comprising of thought in order to accomplish the goal. Finally, practical element refers to specific means, tool, media, material and techniques to concretize the contents through form. Almost all of thoughts and meaning which human being tries to express consist of language. Major elements in sentence include 'subject (omissible)' , 'objects (aim)', 'predicate (formality)', 'complement (means)' and they are composed systematically and hierarchically with rules in sentence. The study compared human activity model with language structure and analyzed their implication with design (aesthetics), which made it possible to propose analytic frameworks for traditional aesthetics. In addition, the study also systematically organized the way to realize traditional aesthetic value in the present context based on the methods developed in this study.

• The Transactions of the Korea Information Processing Society
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• v.7 no.3
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• pp.891-900
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• 2000

A Visual development framework for embedded system is presented based on virtual prototyping. Embedded systems often are used in life critical situation, where reliability is very important. Time_to_market, correctness, user_friendly_design are another features required for embedded system design. However, embedded systems are today designed with an ad hoc approach that is heavily based on earlier experience with similar products. We believe that new design paradigm is needed and it should be based on the use of formal model and visual system to describe the behavior of the system at a high level abstraction. Virtual prototyping has all the required features. It has the following advantages; correct design, clear interface definition, idea experimentation, increased communication. In this paper, we describe the design and implementation of VIP/Sim(Virtual Prototyping Simulator), a visionary development framework for embedded system design. New feature such as state polymorphism is augmented to the de_facto standard formal language, statechart, for enhanced dynamic modeling. Actual design experience with VIP/Sim is also discussed.

• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.1027-1030
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• 2015

하드웨어 디자인 설계에서 초기 단계의 설계 오류 발견은 개발 비용 감소 및 설계 시간 단축 측면에서 그 효과가 매우 크다. 이러한 초기 설계 오류 발견을 위한 대표적인 방법으로는 정형 검증(formal verification)이 있으며, Cadence SMV(Symbolic Model Verifier)는 정형 검증을 위해 Verilog HDL(Hardware Description Language)을 SMV로 자동 변환 해주는 장점이 있지만, 사건 기반 구조(event based structures)의 sensitivity list에 대한 지원을 하지 않는 한계가 있다. 이에 본 논문에서는 Cadence SMV에서 디지털회로(digital circuit) 중 하나인 조합 논리회로(combinational logic circuit)를 sensitivity list가 고려된 검증이 가능하도록 하는 방법을 제안한다. 신뢰성 있는 실험을 위해 본 논문에서는 제안하는 방법의 일반적인 규칙을 도출하였고, 도출된 규칙이 적용된 SMV 파일을 생성하는 자동화 프로그램을 구현하여 실험하였다. 실험결과 제안한 방법을 적용한 경우 기존 Cadence SMV가 발견하지 못한 설계상의 오류를 발견할 수 있었다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.1
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• pp.64-88
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• 2024

Security and reliability are the utmost importance facts in intelligent networked vehicles. Stochastic Petri Net and Z (SPZN) as an excellent formal verification tool for modeling concurrent systems, can effectively handles concurrent operations within a system, establishes relationships among components, and conducts verification and reasoning to ensure the system's safety and reliability in practical applications. However, the application of a system with numerous nodes to Petri Net often leads to the issue of state explosion. To tackle these challenges, a refinement and abstraction method based on SPZN is proposed in this paper. This approach can not only refine and abstract the Stochastic Petri Net but also establish a corresponding relationship with the Z language. In determining the implementation rate of transitions in Stochastic Petri Net, we employ the interval average and weighted average method, which significantly reduces the time and space complexity compared to alternative techniques and is suitable for expert systems at various levels. This reduction facilitates subsequent comprehensive system analysis and module analysis. Furthermore, by analyzing the properties of Markov Chain isomorphism in the case study, recommendations for minimizing system risks in the application of intelligent parking within the intelligent networked vehicle system can be put forward.

• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.512-521
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• 1999

SGML, defined as the ISO 8879, is a meta-language to define a document type, used as basic format for electronic documents. Since an SGML document is composed of a document type definition and a document instance conforms to the definition, it is necessary for SGML document authoring tools to compose and validate document type and document instance. In present, formal models and procedures for SGML documents are not defined, it's not easy to construct such tools. We propose a model of SGML authoring tool consists of SGML parser, document type definition editor, SGML document editor and style editor. We also introduce and implement formal procedure for each component. For user convenience, we adopted icon based visual programming method, and solved the HANGUL problems. The SGML authoring tool is implemented I Windows NT system using java and C++ programming language.

• Journal of Information Processing Systems
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• v.11 no.1
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• pp.22-38
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• 2015

While Modern Standard Arabic is the formal spoken and written language of the Arab world; dialects are the major communication mode for everyday life. Therefore, identifying a speaker's dialect is critical in the Arabic-speaking world for speech processing tasks, such as automatic speech recognition or identification. In this paper, we examine two approaches that reduce the Universal Background Model (UBM) in the automatic dialect identification system across the five following Arabic Maghreb dialects: Moroccan, Tunisian, and 3 dialects of the western (Oranian), central (Algiersian), and eastern (Constantinian) regions of Algeria. We applied our approaches to the Maghreb dialect detection domain that contains a collection of 10-second utterances and we compared the performance precision gained against the dialect samples from a baseline GMM-UBM system and the ones from our own improved GMM-UBM system that uses a Reduced UBM algorithm. Our experiments show that our approaches significantly improve identification performance over purely acoustic features with an identification rate of 80.49%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.29 no.4
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• pp.739-751
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• 2019

Security in embedded devices has become a significant issue. Threats on the sup-ply chain, like using counterfeit components or inserting backdoors intentionally are one of the most significant issues in embedded devices security. To mitigate these threats, high-level security evaluation and certification more than EAL (Evaluation Assurance Level) 5 on CC (Common Criteria) are necessary on hardware components, especially on the cryptographic module such as AES. High-level security evaluation and certification require detecting covert channel such as backdoors on the cryptographic module. However, previous studies have a limitation that they cannot detect some kinds of backdoors which leak the in-formation recovering a secret key on the cryptographic module. In this paper, we present an expanded definition of backdoor on hardware AES module and show how to detect the backdoor which is never detected in Verilog HDL using model checker NuSMV.