• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2005년도 제17회 워크샵 및 추계학술대회
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• pp.665-665
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• 2005

The existing DSP for utility interactive photovoltaic generation system control generally uses floating point process type. Because it is easy to use for number crunching, however, it is too late and too expensive. Fixed point process DSP TMS320F2812, has high control speed and is rather inexpensive. A very complicated real system can be simulated using hardware-in-the-loop (HIL) system in a virtual environment Therefore, HIL system can speed up research and development process with a little effort. Also current DSP for utility interactive photovoltaic generation system adopts floating point process type, which is easy to use for number crunching. However, fixed point process DSF, TMS320F2812, has high control speed and is rather inexpensive. This paper presents more efficient method for MPPT control using TMS320F2812 along with HIL System.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권4호
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• pp.234-239
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• 2006

In the past decade, several tools have been developed to automate the floating-point to fixed-point conversion for DSP systems. In the conversion process, a number of scaling shifts are introduced, and they inevitably alter the original code sequence. Recently, we have observed that a compiler can often be adversely affected by this alteration, and consequently fails to generate efficient machine code for its target processor. In this paper, we present an optimization technique that safely migrates scaling shifts to other places within the code so that the compiler can produce better-quality code. We consider our technique to be safe in that it does not introduce new overflows, yet preserving the original SQNR. The experiments on a commercial fixed-point DSP processor exhibit that our technique is effective enough to achieve tangible improvement on code size and speed for a set of benchmarks.

• Korean Management Science Review
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• 제26권1호
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• pp.197-208
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• 2009

In this paper, we study stochastic maximal covering location problem considering floating population. Traditional maximal covering location problem assumed that number of populations at demand point is already known and fixed. In this manner, someone who try to solve real world maximal covering location problem must consider administrative population as a population at demand point. But, after observing floating population, appliance of population in steady-state is more reasonable. In this paper, we suggest revised numerical model of maximal covering location problem. We suggest heuristic methodology to solve large scale problem by using genetic algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제21권5호
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

• Journal of Korea Multimedia Society
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• 제11권6호
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• pp.816-827
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• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2072-2075
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• 2003

This paper is studied the high speed processing moving picture encodec to compress and encode a moving picture by real time. This is used the new motion vector search algorithm with smallest search point in H.263 encodec, and is applied the integer DCT for the encodec by converting a moving picture. The integer DCT behaves DCT by the addition operation of the integer using WHT and a integer lifting than conventional DCT that needs the multiplication operation of a floating point number. Therefore, the integer DCT can reduce the operation amount than basis DCT with having an equal PSNR because the multiplication operation of a floating point number does not need.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제11권1호
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• pp.46-55
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• 2007

The Newton-Raphson's algorithm for finding a floating point reciprocal and inverse square root calculates the result by performing a fixed number of multiplications. In this paper, an improved Newton-Raphson's algorithm is proposed, that performs multiplications a variable number. Since the number of multiplications performed by the proposed algorithm is dependent on the input values, the average number of multiplications per an operation is derived from many reciprocal and inverse square tables with varying sizes. The superiority of this algorithm is proved by comparing this average number with the fixed number of multiplications of the conventional algorithm. Since the proposed algorithm only performs the multiplications until the error gets smaller than a given value, it can be used to improve the performance of a reciprocal and inverse square root unit. Also, it can be used to construct optimized approximate tables. The results of this paper can be applied to many areas that utilize floating point numbers, such as digital signal processing, computer graphics, multimedia, scientific computing, etc.

• Journal of Microbiology
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• 제45권2호
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• pp.122-127
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• 2007

Factors indicating culture status of two Spirulina platensis strains were monitored in a batch mode cultivation for 36 days. Changing mode in all factors showed a common turning point, indicating shift of cell or culture status. Mean biomass productivity was highly sustained until day 22, chlorophyll a concentration peaked on day 22, pH value was > 12 on day 22, coil number was abruptly shortened on day 22, and floating activity was sustained at greater than 79% after day 22, indicating that day 22 is a criterion reflecting phase-transfer in cell physiology in a batch culture system. Many of these changes may have been caused by increased pH, suggesting that pH control is essential for mass production of S. platensis. Fluctuations in floating activity were likely induced by the number of cellular gas vacuoles. Consequently, coil number per trichome and floating activity of S. platensis could readily act as simple indicators for determination of culture status or harvesting time of cells.

• Journal of the Institute of Convergence Signal Processing
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• 제12권2호
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• pp.139-144
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• 2011

The modern digital logic technology does not yet satisfy the speed requirements of real-time DSP circuits due to synchronized operation of multiplication and accumulation. This operation degrades DSP performance. Therefore, the double-base number system (DBNS) has emerged in DSP system as an alternative methodology because of fast multiplication and hardware simplicity. In this paper, authors propose a novel multiplication architecture. One operand is an output of a flash analog-to-digital converter (ADC) in DBNS format, while the other operand is a coefficient in the IEEE standard floating-point number format. The DBNS digital output from ADC is produced through a new double base number encoder (DBNE). The multiplied output is in the format of the IEEE standard floating-point number (FPNS). The proposed circuits process multiplication and conversion together. Compared to a typical multiplier that uses the FPNS, the proposed multiplier also consumes 45% less gates, and 44% faster than the FPNS multiplier on Spartan-3 FPGA board. The design is verified with FIR filter applications.

• Proceedings of the Korea Water Resources Association Conference
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• 한국수자원학회 2017년도 학술발표회
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• pp.514-514
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• 2017

Floating breakwaters were treated as solid bodies without any perforation in previous studies. In this study, however, a floating breakwater is perforated to allow the partial absorption of the energy produced by incident waves and an air chamber is placed in the upper part to control the breakwater draft. A series of laboratory experiments for a floating breakwater installed with a mooring system are carried out. In general, a mooring system can be classified by the number of mooring points, the shape of the mooring lines, and the degree of line tension. In this study, a four-point mooring is employed since it is relatively easier to analyze the measured results. Furthermore, both the tension-leg and the catenary mooring systems have been adopted to compare the performance of the system. In laboratory experiments, the hydraulic characteristics of a floating breakwater were obtained and analyzed in detail. Also, a hydraulic model test was carried out on variable changes by changing the mooring angle and thickness of perforated wall. A hydraulic model was designed to produce wave energy by generating a vortex with the existing reflection method. Analysis on wave changes was conducted and the flow field around the floating breakwater and draft area, which have elastic behavior, was collected using the PIV system. From the test results the strong vortex was identified in the draft area of the perforated both-sides-type floating breakwater. Also, the wave control performance of the floating breakwater was improved due to the vortex produced as the tension in the mooring line decreased.