• Korean Management Science Review
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• v.26 no.1
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• pp.197-208
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• 2009

In this paper, we study stochastic maximal covering location problem considering floating population. Traditional maximal covering location problem assumed that number of populations at demand point is already known and fixed. In this manner, someone who try to solve real world maximal covering location problem must consider administrative population as a population at demand point. But, after observing floating population, appliance of population in steady-state is more reasonable. In this paper, we suggest revised numerical model of maximal covering location problem. We suggest heuristic methodology to solve large scale problem by using genetic algorithm.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.9
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• pp.33-42
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• 1997

Fixed-point optimization utility software that can aid scaling and wordlength determination of digital signal processign algorithms written in C or C$\^$++/ language is developed. This utility consists of two programs: the range estimator and the fixed-point simulator. The former estimates the ranges of floating-point variables for automatic scaling purpose, and the latter translates floating-point programs into fixed-point equivalents for evaluating te fixed-point performance by simulation. By exploiting the operator overloading characteristics of C$\^$++/ language, the range estimation and the fixed-point simulation can be conducted just by modifying the variable declaration of the original program. This utility is easily applicable to nearly all types of digital signal processing programs including non-linear, time-varying, multi-rate, and multi-dimensional signal processing algorithms. In addition, this software can be used for comparing the fixed-point characteristics of different implementation architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.659-662
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• 1999

In this paper we implement MP3 encoder based on integer operations. To implement MP3 encoder presented in ［1］, floating-point operations are required. But we devise an MP3 encoding method which is based on integer operations. To verify the method presented in this paper, we implement MP3 encoder using ARM processor. In this paper we present the method to change floating point operations into integer operations, and the ARM assembly programming technique to implement fast MP3 encoder. The MP3 encoder implement using integer processor consumes less power than the encoder implemented using floating-point processor. So the encoder implemented in this paper is suitable lot portable applications which requires low power consumption.

• Journal of IKEEE
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• v.14 no.2
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• pp.64-68
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• 2010

This paper proposes efficient log and exponent calculation methods using a dual phase instruction set without additional ALU unit for a mobile enviroment. Using the Dual Phase Instruction set, it extracts exponent and mantissa from expression of floating point and calculates 24bit single precision floating point of log approximation using the Taylor series expansion algorithm. And with dual phase instruction set, it reduces instruction excution cycles. The proposed Dual Phase architecture reduces the performance degradation and maintain smaller size.

• Journal of Korea Multimedia Society
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• v.11 no.6
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• pp.816-827
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• 2008

In this paper, two-stage pipelined floating-point arithmetic unit (FP-AU) is designed. The FP-AU processor supports seventeen operations to apply 3D graphics processor and has area-efficient and low-latency architecture that makes use of modified dual-path computation scheme, new normalization circuit, and modified compound adder based on flagged prefix adder. The FP-AU has about 4-ns delay time at logic synthesis condition using $0.18{\mu}m$ CMOS standard cell library and consists of about 5,930 gates. Because it has 250 MFLOPS execution rate and supports saturated arithmetic including a number of graphics-oriented operations, it is applicable to mobile 3D graphics accelerator efficiently.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.3-4
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• 2011

This paper presents a survey of floating power supply based on bootstrap operation for three-level voltage-source inverters. The floating power supply for upper switches is achieved by the bootstrap capacitor charged during on-time of the switch underneath. Hence, a large number of bulky isolated DC/DC power supplies for each gate driver are reduced. The Pspice simulation results show the behavior of bootstrap devices and the performance of bootstrap capacitor voltage.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.05a
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• pp.293-295
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• 2004

In this research, we suggest the effective technique that the thickness of slab isn't increased, and considering proper shock absorbing material and supporting point, we make the floating floor which has multi-supporting system floating floor. As the result, it is effective in reduction of heavy weight system as well as one of light weight

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2003.11a
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• pp.928-931
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• 2003

In this research, we suggest the effective technique that the thickness of slab isn't increased, and considering proper shock absorbing material and supporting point, we make the floating floor which has multi-supporting system floating nut. As the result, it is effective in reduction of heavy weight system as well as one of light weight