• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.55-59
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• 2003

In this paper, we estimate the performance requirements of general-purpose DSP for Carrier Recovery of OFDM DVB-T receiver. Firstly, we transported the designed fixed-point OFDM DVB-T model to a floating-point software model written in C. Then, we measured the number of instruction cycles required for operation of Carrier Recovery in time. We use SignalMaster$\^$TM/ DSP platform of LYRtech Inc. as a environment of estimation, and Simulink$\^$TM/ as a graphical interface, Code Composer StudioTM of TI as profiler and compiler, and SPW$\^$TM/ for presenting functional reliability and comparing the performance distortion with fixed-point model. As a result, we show the required number of DSPs in our DSP-based system, and introduce the need of Multi-DSP-based system.

• Journal of the Semiconductor & Display Technology
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• v.3 no.1
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• pp.21-26
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• 2004

Recently with the development of power switching device and DSP which has peripheral devices to control AC servo system, the servo technology has met a new development opportunity. Those things make it possible to reduce the time of developing a AC servo system. Fixed point DSP such as TMS320F240x, and TMS320F28x series have a disadvantage in calculating floating number where TMS320C32 or TMS320C31 are floating point DSP. However they usually become a complex hardware system to implement the AC servo system and it increases the cost. In this study, a DSP based AC servo system with a 3-phase PMSM is proposed. The newly produced DSP TMX320F28l2-version C which has the performance of fast speed, 150MIPS, and a rich peripheral interface such as a 12bit high speed AD converter, QEP(Quadrature Encoder Pulse) circuit, PDPINT(Power Drive Protect Interrupt), SVPWM module and dead time module are used. This paper presents a method to overcome fixed point calculating using scaling all parameters. Also space vector pulse width modulation (SVPWM) using off-set voltage and a digital PI control are implemented to the servo system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.3
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• pp.563-569
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• 2007

As the mobile communication and the semiconductor technology is improved continuously, mobile contents such as the multimedia service and the 2D/3D graphics which require high level graphics are serviced recently. Mobile chips should consume small die area and low power. In this paper, we design a truncated floating-point multiplier that is useful for the 2D/3D vector graphics in mobile devices. The truncated multiplier is based on the radix-4 Booth's encoding algorithm and a truncation algorithm is used to achieve small area and low power. The average percent error of the multiplier is as small as 0.00003% and neglectable for mobile applications. The synthesis result using 0.35um CMOS cell library shows that the number of gates for the truncated multiplier is only 33.8 percent of the conventional radix-4 Booth's multiplier.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.37 no.5
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• pp.7-16
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• 2000

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It performed the division and square-toot by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.12
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.10A
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• pp.1764-1771
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• 2001

It has developed a PCM signal acquisition(PCMA) system which can analyze status of signals in order to establish rapid diagnosing in TDX-families signaling service equipment. We develop the quick Fourier transform(QFT) for length 2$\^$M/ data to analyze the power spectral of the PCMA system. This algorithm can reduces the number of floating-point operations necessary to compute the DFT by a factor of two or four over direct methods or Goertzels method for prime lengths. In the experimental results, the system classifies the type of signals and finally discriminates the digit.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.55-65
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• 1995

Existing multiple-row downdating algorithms have adopted a CFD(Cholesky Factor Downdating) that recursively downdates one row at a time. The CFD based algorithm requires 5/2p $n^{2}$ flops(floating point operations) downdating a p$\times$n observation matrix $Z^{T}$ . On the other hands, a HCFD(Hybrid CFD) based algorithm we propose in this paper, requires p $n^{2}$＋6/5 $n^{3}$ flops v hen p$\geq$n. Such a HCFD based algorithm factorizes $Z^{T}$ at first, such that $Z^{T}$ = $Q_{z}$ RT/Z, and then applies the CFD onto the upper triangular matrix Rt/z, so that the total number of floating point operations for downdating $Z^{T}$ would be significantly reduced compared with that of the CFD based algorithm. Benchmark tests on the Sun SPARC/2 and the Tolerant System also show that performance of the HCFD based algorithm is superior to that of the CFD based algorithm, especially when the number of rows of the observation matrix is large.rge.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.238-241
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• 2000

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA. (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL models. We have peformed logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5 $\mu\textrm{m}$ standard cell library (STD80). The total number of gates is about 130,000.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.57-60
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• 2005

The existing DSP for utility interactive photovoltaic generation system control, generally uses floating point process type. Because it is easy to use for number crunching, However it is too late and too expensive. fixed point process DSP, TMS320F2812, has high control speed and is rather inexpensive. This paper presents more efficient method for MPPT control using TMS320F2812.