• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.6
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• pp.25-34
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• 2000

This paper describes design of a 250-Mbps 10-channel optical receiver array for parallel optical interconnection with the general-purpose CMOS technology The optical receiver is one of the most important building blocks to determine performance of the parallel optical interconnection system. The chip in CMOS technology makes it possible to implement the cost-effective system also. Each data channel consists of analog front-end including the integrated photo-detector and amplifier chain, digital block with D-FF and off-chip driver. In addition, the chip includes PLL (Phase-Lock Loop) for synchronous data recovery. The chip was fabricated in a 0.65-${\mu}{\textrm}{m}$ 2-poly, 2-metal CMOS technology. Power dissipation of each channel is 330㎽ for $\pm$2.5V supply.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.29-36
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• 2004

A flexible packaging scheme, which includes chip packaging, has been developed using a thinned silicon chip. Mechanical characteristics of thinned silicon chips are examined by bending tests and finite element analysis. Thinned silicon chips (t<30 $\mu\textrm{m}$) are fabricated by chemical etching process to avoid possible surface damages on them. And the chips are stacked directly on $Kapton^{Kapton}$film by thermal compressive bonding. The low height difference between the thinned silicon chip and $Kapton^{Kapton}$film allows electroplating for electrical interconnection method. Because the 'Chip' is embedded in the flexible substrate, higher packaging density and wearability can be achieved by maximized usable packaging area.

• Journal of Welding and Joining
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• v.24 no.2
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• pp.64-70
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• 2006

The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

• Korean Journal of Materials Research
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• v.10 no.12
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• pp.853-863
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• 2000

In this study, a new UBM materials system for solder flip chip interconnection of Cu pads were investigated using electroless copper (E-Cu) and electroless nickel (E-Ni) plating method. The interfacial reaction between several UBM structures and Sn-36Pb-2Ag solder and its effect on solder bump joint mechanical reliability were investigated to optimife the UBM materials design for solder bump on Cu pads. Fer the E-Cu UBM, continuous coarse scallop-like $Cu_{6}$ $Sn_{5}$ , intermetallic compound (IMC) was formed at the solder/E-Cu interface, and bump fracture occurred this interface under relative small load. In contrast, Fer the E-Ni/E-Cu UBM, it was observed that E-Ni effectively limited the growth of IMC at the interface, and the Polygonal $Ni_3$$Sn_4$ IMC was formed because of crystallographic mismatch between monoclinic $Ni_3$$Sn_4$ and amorphous E-Ni phase. Consequently, relatively higher bump adhesion strength was observed at E-Ni/E-Cu UBM than E-Cu UBM. As a result, it was fecund that E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on CU PadS.

• Korean Journal of Materials Research
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• v.9 no.3
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• pp.288-294
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• 1999

In the flip chip interconnection using solder bump, the Under Bump Metallurgy (UBM) is required to perform multiple functions in its conversion of an aluminum bond pad to a solderable surface. In this study, various UBM systems such as $Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 5\mu\textrm{m}, Al 1\mu\textrm{m} / Ti 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}, al 1\mu\textrm{m}/Ni 0.2\mu\textrm{m} / Cu 1\mu\textrm{m} and Al 1\mu\textrm{m}/Pd 0.2\mu\textrm{m} / Cu 1\mu\textrm{m}$ for flip chip interconnection using the low melting point eutectic 63Sn-37Pb solder were investigated and compared to their metallurgical properties. $100\mu\textrm{m}$ size bumps were prepared for using an electroplating process. The effects of the number of reflows and aging time on the growth of intermetallic compounds(IMC) were investigated. $Cu_6Sn_5$ and $Cu_3Sn$ IMC were abserved after aging treatment in the UBM system with thick coper $(Al 1\mu\textrm{m}/Ti 0.2\mu\textrm{m}/Cu 5\mu\textrm{m})$. However only the $Cu_6Sn_5$ was detected in the UBM system with $1\mu\textrm{m}$ thick copper even after 2 reflow and 7 day aging at $150^{\circ}C$. Complete Cu consumption by Cu-Sn IMC growth gives rise to a direct contact between solder inner layer such as Ti, Ni and Pd, and hence to possibly cause reactions between two of them. In this study, however, only for the Pd case, IMC of PdSn. was observed by Cu consumption. UBM interfacial reactions with s이der affected the adhesion strength ot s이der balls after s이der reflow and annealing treatment.

• ETRI Journal
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• v.37 no.2
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• pp.387-394
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• 2015

A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than $150^{\circ}C$. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than $150^{\circ}C$. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a $20{\mu}m$ pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at $130^{\circ}C$.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.11-15
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• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.

• Proceedings of the KWS Conference
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• 2010.05a
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• pp.78-78
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• 2010

모바일 정보통신기기를 중심으로 패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있고 있으며 접속피치의 미세화에 따라 솔더 및 언더필을 사용하는 C4 공법보다 ACA(Anisotropic Conductive Adhesive), NCA (Non-conductive Adhesive) 등의 접착제를 이용하는 칩본딩 공법에 대한 요구가 증가하고 있다. 특히, NCA 공법의 경우 산업 현장의 대량생산에 대응하기 위해서는 접착제의 속경화 특성이 요구되어 진다. 일반적으로 접착제의 경화거동은 DSC(Differential Scanning Calorimeter)를 사용해 확인하지만, 수초 이내에 경화되는 접착제의 경우는 적용되기 어렵다. 본 연구에서는 이러한 전자패키지용 접착제의 속경화 거동을 효과적으로 평가할 수 있는 방법을 조사 하였다. 실험에서 사용된 접착제는 에폭시계 레진 기반에 이미다졸계 경화제를 사용한 기본적인 포뮬레이션을 사용하였고, 경화시간은 160^{\circ}C에서 1분 이내에 경화되는 특성을 가지고 있다. 경화 거동을 확인하기 위해서 isothermal DSC와 DEA(Dielectric Analysis)의 두가지 방법을 사용해 비교하였다. 두 실험 방법 모두 $160^{\circ}C$를 유지하며 경화 거동을 확인하였고, DoC(Degree of Cure)의 측정오차를 비교 분석하였다. DEA는 이온 모빌리티 변화에 따른 유전손실율을 측정하는 방법으로 80~90% 이후의 경화도는 측정되지 않았지만, 수초 이내에 경화되는 속경화 특성을 평가하기에 적합한 것으로 확인되었다.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.35-41
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• 2002

Flip-chip interconnection that uses solder bump is an essential technology to improve the performance of micro-electronics which require higher working speed, higher density, and smaller size. In this paper, the shear strength of Cr/Cr-Cu/Cu UBM structure of the high-melting solder bump and that of low-melting solder bump after aging is evaluated. Observe intermetallic compound and bump joint condition at the interface between solder and UBM by SEM and TEM. And analyze the shear load concentrated to bump applying finite element analysis. As a result of experiment, the maximum shear strength of Sn-97wt%Pb which was treated 900 hrs aging has been decreased as 25% and Sn-37wt%Pb sample has been decreased as 20%. By the aging process, the growth of $Cu_6/Sn_5$ and $Cu_3Sn$ is ascertained. And the tendency of crack path movement that is interior of a solder to intermetallic compound interface is found.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.7
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• pp.496-499
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• 2012

Modified structure of copper pillar bump which has trapezoidal cross section on the top region is suggested with simulation results and concept of fabrication process. Due to the large surface area of joint region between bump and solder in suggested structure, electro-migration effect can be reduced. Reduction of electro-migration is related with current density and joule heating in bump and investigated with finite element methods with variation of dimensional parameters. Mechanical characteristics are also investigated with comparing modified copper pillar bump and conventional copper pillar bump.