• 한국운동역학회지
• /
• 제21권1호
• /
• pp.9-16
• /
• 2011

The purpose of this study is to analyze the effects of both various shoe types and bare feet on ground reaction force while walking. Ten first-year female university students were selected. A force platform(Kistler, Germany) was used to measure ground reaction force. Six types of shoe were tested: flip flops, canvas shoes, running shoes, elevated forefoot walking shoes, elevated midfoot walking shoes, and five-toed shoes. The control group was barefooted. Only vertical passive/active ground reaction force variables were analyzed. The statistical analysis was carried out using the SAS 9.1.2 package, specifically ANOVA, and Tukey for the post hoc. The five-toed shoe had the highest maximum passive force value; while the running shoe had the lowest. The first active loading rate for running shoes was the highest; meanwhile, bare feet, the five-toed shoe, and the elevated fore foot walking shoe was the lowest. Although barefoot movement or movement in five toed shoes increases impact, it also allows for full movement of the foot. This in turn allows the foot arch to work properly, fully flexing along three arches(transverse, lateral, medial), facilitating braking force and initiating forward movement as the tendons, ligaments, and muscles of the arch flex back into shape. In contrast movement in padded shoes have a tendency to pound their feet into the ground. This pounding action can result in greater foot instability, which would account for the higher loading rates for the first active peak for padded shoes.

• 전자공학회논문지A
• /
• 제33A권11호
• /
• pp.140-151
• /
• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• 전자공학회논문지B
• /
• 제33B권1호
• /
• pp.79-86
• /
• 1996

본 논문은 가변길이코드의 encoding/decoding를 위한 간단하고도 메모리 측면에서 효율적인 구조를 제안한다. MPEG1 DCT계수를 encoding/decoding함으로써 구현한 본 구조에서 114개의 DCT계수를 메모리 매핑하는데 최소인 7비트의 어드레스가 할당되도록 하였고, 직렬-병렬 및 병렬-직렬 변환용 쉬프트 레지스터와 code mapping ROM을 결합시킨 구조로써 최소의 플립플롭 및 메모리를 사용하여 구현하였다. 속도측면에선 COMPASS tool(0.8${\mu}m$ CMOS technology standard cells)을 사용해서 시뮬레이션 해본 결과 encoding/decoding의 경우 모두 50Mbps의 동작속도를 얻을 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제15권2호
• /
• pp.168-176
• /
• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
• /
• pp.267-269
• /
• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• Nuclear Engineering and Technology
• /
• 제48권5호
• /
• pp.1192-1205
• /
• 2016

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

• 한국통신학회논문지
• /
• 제33권1C호
• /
• pp.140-148
• /
• 2008

타입 II ONB(optimal normal basis)의 자기쌍대성(self duality)을 이용하여 낮은 하드웨어 복잡도와 작은 지연시간을 가지는 GF($2^m$)상의 비트 패러럴, 시리얼 시스톨릭 어레이를 제안하였다. 제안된 곱셈기는 m+1의 지연시간을 가지며 각 셀은 5개의 래치(플립-플롭)로 구성된다. 제안된 어레이는 다른 어레이와 비교하여 공간 복잡도와 지연시간을 줄임을 알 수 있다.

• International Journal of Computer Science & Network Security
• /
• 제22권9호
• /
• pp.414-426
• /
• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• 반도체디스플레이기술학회지
• /
• 제21권4호
• /
• pp.27-32
• /
• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• 센서학회지
• /
• 제32권4호
• /
• pp.246-251
• /
• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.