• 한국산업융합학회 논문집
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• 제3권1호
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• pp.69-75
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• 2000

Multichip packages are comprised of dissimilar materials which expand at different rates on heating. The differential expansion must be accommodated by the various structural elements of the package. A types of heat exposures occur operation cycles. This study presents a finite element analysis simulation of flip-chip among multichip. The effects of geometries and material properties on the reliability were estimated during the analysis of temperature and thermal stress of flip-chip. From the results, it could be obtained that the more significant parameters to the reliability of flip-chip arc chip power cycle, heat convection and height of solder bump.

• 대한금속재료학회지
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• 제50권10호
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• pp.785-792
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• 2012

A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from $135m{\Omega}$ to $79m{\Omega}$ by increasing the flip chip bonding pressure from 85 MPa to 185 MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%.

• 마이크로전자및패키징학회지
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• 제20권4호
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• pp.17-23
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• 2013

신축성 전자패키징 기술개발을 위한 기초연구로서 Cu/Sn 범프에 CNT-Ag 복합패드를 형성한 칩을 이방성 전도접착제를 사용하여 플립칩 본딩한 후, CNT-Ag 복합패드의 유무 및 본딩압력에 따른 플립칩 접속부의 접속저항을 측정하였다. CNT-Ag 복합패드가 형성된 Cu/Sn 칩 범프를 25MPa과 50MPa의 본딩압력으로 플립칩 본딩한 시편들은 접속저항이 너무 높아 측정이 안되었으며, 100MPa의 본딩압력으로 플립칩 본딩한 시편은 $213m{\Omega}$의 평균 접속저항을 나타내었다. 이에 비해 CNT-Ag 복합패드가 없는 Cu/Sn 칩 범프를 사용하여 25MPa, 50 MPa 및 100 MPa의 본딩압력으로 플립칩 본딩한 시편은 각기 $1370m{\Omega}$, $372m{\Omega}$ 및 $112m{\Omega}$의 평균 접속저항을 나타내었다.

• 반도체디스플레이기술학회지
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• 제14권3호
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• pp.13-22
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• 2015

LED (Light Emitting Diode) lighting is gaining more and more market penetration as one of the global warming countermeasures. LED is the next generation of fusion source composed of epi/chip/packaging of semiconductor process technology and optical/information/communication technology. LED has been applied to the existing industry areas, for example, automobiles, TVs, smartphones, laptops, refrigerators and street lamps. Therefore, LED makers have been striving to achieve the leading position in the global competition through development of core source technologies even before the promotion and adoption of LED technology as the next generation growth engine with eco-friendly characteristics. However, there has been a point of view on the cost compared to conventional lighting as a large obstacle to market penetration of LED. Therefore, companies are developing a Chip-Scale Packaging (CSP) LED technology to improve performance and reduce manufacturing costs. In this study, we perform patent analysis associated with Flip-Chip CSP LED and flow chart for promising technology forecasting. Based on our analysis, we select key patents and key patent players to derive the business strategy for the business success of Flip-Chip CSP PKG LED products.

• 한국전기전자재료학회논문지
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• 제28권10호
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• pp.676-681
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• 2015

Recently many studies being carried out to increase the light efficiency of LED. The external quantum efficiency of LED, generally the light efficiency, is determined by the internal quantum efficiency and the light extraction efficiency. The internal quantum efficiency of LED was already reached to more than 90%, but the light extraction efficiency is still insufficient compared with the internal quantum efficiency because the total internal reflection is generated in the interface between the LED chip and air. Thus, we studied about flip chip LED with PSS and performed the optical simulation which find more optimized PSS for flip chip LED to increase the light extraction efficiency. Decreasing of the total internal reflection and effect of diffused reflection according to PSS improved the light extraction efficiency. To get more higher the efficiency, we simulated flip chip with PSS that the parameters are arrangement, edge spacing, radius, height and shape of PSS.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.763-768
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• 2005

Bare-chip packaging becomes more popular along with the miniaturization of IT components. In this paper, we have studied flip-chip process, and developed automated bonding system. Among the several bonding method, NCP bonding is chosen and batch-type equipment is manufactured. The dual optics and vision system aligns the chip with the substrate. The bonding head equipped with temperature and force controllers bonds the chip. The system can be easily modified for other bonding methods such as ACF In bonding process, the bonding forte and temperature are known as the most dominant bonding parameters. A parametric study is performed for these two parameters. For the test sample, we used standard flip-chip test kit which consists of FR4 boards and dummy flip-chips. The bonding test was performed fur two types of flip-chips with different chip size and lead pitch. The bonding temperatures are chosen between $25^{\circ}C\;to\;300^{\circ}C$. The bonding forces are chosen between 5N and 300N. The bonding strength is checked using bonding force tester. After the bonding force test, the samples are examined by microscope to determine the failure mode. The relations between the bonding strength and the bonding parameters are analyzed and compared with bonding models. Finally, the most suitable bonding condition is suggested in terms of temperature and force.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.519-520
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• 2008

• 마이크로전자및패키징학회지
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• 제7권1호
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• pp.61-73
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.469-470
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• 2007

• 한국전자파학회논문지
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• 제25권4호
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• pp.483-486
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• 2014

일반적으로 플립 칩은 와이어 본딩에 비해 신호 무결성을 저해하는 기생 성분이 작지만, 60 GHz 대역에서는 설계하기에 따라서 2 dB 이상의 삽입 손실 차이가 난다. 본 논문에서는 플립 칩 구조의 여러 설계 변수들에 따라 삽입 손실이 어떻게 변하는 지를 분석함으로써 설계를 최적화하는 방법을 제시한다.