• ETRI Journal
• /
• 제25권3호
• /
• pp.187-194
• /
• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• ETRI Journal
• /
• 제30권2호
• /
• pp.275-281
• /
• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• 전기학회논문지P
• /
• 제53권4호
• /
• pp.210-215
• /
• 2004

This paper proposes an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph, a Boolean function is derived, whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This function is then used to determine the minimum cost feedback vertex set. Even though computing the minimum cost satisfying assignment for a Boolean function remains an NP-hard problem, it is possible to exploit the advances made in the area of Boolean function representation in logic synthesis to tackle this problem efficiently in practice for even reasonably large sized graphs. The algorithm has obvious application in flip-flop selection for partial scan. The algorithm proposed in this paper is the first to obtain the MFVS solutions for many benchmark circuits.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2004년도 전력전자학술대회 논문집(1)
• /
• pp.105-108
• /
• 2004

In this paper, the simple analog MPPT (Maximum Power Point Tracking) algorithm is proposed for the solar array of KOMPSAT (Korea Multi-Purpose Satellite). This method doesn't need any calculation of power by multiplication of voltage and current and a measurement of the solar array temperature. It is consist of only two sample and hold circuits, two comparators, a flip-flop, and an integrator. The proposed MPPT algorithm is verified by the simulation for the 100[W] solar array.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
• /
• pp.1467-1470
• /
• 1987

This paper proposes a functional simulation algorithm which decrease the internal memory space and run time in simulation of VLSI. Flip-flop, register, ram, rom, ic and fun are described as functional elements in the simulator. Especially icf is made as new functional element by combining the gate and the functional element, therefore icf is used efficiently in simulation of VLSI. The proposed algorithm is implemented on PC-AT(MS-DOS) in by Prolog-1.

• 한국초전도학회:학술대회논문집
• /
• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
• /
• pp.48-53
• /
• 1999

We demonstrate small-scale high-T$_c$ superconductor RSFQ(Rapid Single Flux Quantum) circuits using multilayer bicrystal technology. An RSFQ balanced comparator is demonstrated with good current resolution, and its operating conditions are discussed in some detail. A single-loop delta-sigma modulator is realized adding a feedback loop to the comparator. The effect of the feedback is confirmed by dc measurement and simulation. A design of an RSFQ toggle flip-flop with the same multilayer bicrystal technology is suggested.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.433-434
• /
• 2008

In this paper, we present an improved design of the conventional ARM7 processor. It is based on the flip-flop to improve the pipeline performance of the processor. Also for improving the performance, the optimization of functional blocks and a multiplier is carried out. According to the experimental results, the maximum delay-time of functional blocks and the execution cycle of a multiplier is reduced by 33% and 2 cycles compared with a conventional design, respectively. Therefore, it leads to improve an operation speed about 30%.

• 전자공학회논문지A
• /
• 제31A권2호
• /
• pp.75-80
• /
• 1994

AlAs/GaAs/AlAs RTDs(Resonant Tunneling Diodes) are fabricated and current-voltage properties of them are measured. At room temperature, peak to valley ratio is 2.4 NOT.AND.OR logic gates and Flip-Flop are fabricated using the bistable characteristics of RTDs. Although NOT.AND.OR logic gates need 5~8 transistors. only one RTD is sufficient to fabricate the logic gates. Since the switching time is very short(<10$^12$sec), it is possible to drive the semiconductor circuits fast and integrate them very large. And it is convinced the possibility of integrating RTDs to multilevel logic circuits by observing two peaks of similar current in the serial connection of two RTDs.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권4호
• /
• pp.215-220
• /
• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• 한국초전도ㆍ저온공학회논문지
• /
• 제4권1호
• /
• pp.17-20
• /
• 2002

A complex single flux quantum(SFQ) circuit could be made up of various elementary cells such as JTL(Josephson transmission line), Splitter, XOR, DC/SFQ, SFQ/DC, T flip-flop, ‥‥, etc. In this work, we have designed and simulated a SFQ circuit, which consists of DC/SFQ, JTL and SFQ/DC, based on Nb/AlO$_{x}$Nb Josephson junction technology From the simulation, we could obtain the margins for various circuit parameters. And also we have successfully operated the circuit, which was fabricated with the same design, up to the input signal frequency of about 20 GHz.z.