• Transactions on Electrical and Electronic Materials
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• 제9권1호
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 추계기술심포지움논문집
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• pp.39-47
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• 2002

Heat is always the root of stress acting upon the electronic package, regardless of the heat due to the device itself during operation or working under the adverse environment. Due to the significant mismatch in coefficient of thermal expansion (CTE) and the thermal conductivity (K) of the packaging components, on one hand intensive research has been conducted in order to enhance the device reliability by minimizing the mechanical stressing and deformation within the package. On the other hand the effectiveness of different thermal enhancements are pursued to dissipate the heat to avoid the overheating of the device. However, the interactions between the thermal-mechanical loading has not yet been address fully. in articular when the temperature gradient is considered within the package. To address the interactions between the thermal loading upon the mechanical stressing condition. coupled-field analysis is performed to account the interaction between the thermal and mechanical stress distribution. Furthermore, process induced defects are also incorporated into the analysis to determine the effects on thermal conducting path as well as the mechanical stress distribution. It is concluded that it feasible to consider the thermal gradient within the package accompanied with the mechanical analysis, and the subsequent effects of the inherent defects on the overall structural integrity of the package are discussed.

• 대한전자공학회논문지SD
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• 제43권9호
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• pp.64-68
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• 2006

본 연구에서는 Si bump를 이용해 기판의 기계적, 열적 특성을 개선한 MCM-D 기판공정을 개발하였고, 이를 system-on-package(SOP)-D개념의 system 구현에 적용하고자 하였다. 이 과정에서 밀리미터파 대역에 적용될 수 있는 필터를 설계하고 구현하여 그 특성을 관찰하였다. 두 가지 형태의 필터를 구현하였는데 첫 번째는 공진기간의 커플링을 이용한 구조로서 2층의 금속층과 3층의 유전체(BCB)를 이용하였다. 구현된 필터 특성은 중심주파수 55 GHz에서의 삽입손실이 2.6 dB이고 군지연이 0.06 ns정도로 우수한 특성을 나타내었다. 또한 일반적으로 알려진coupled line 형태의 필터를 구현하였는데 삽입손실이 3 dB, 군지연이 0.1 ns정도의 특성을 나타내었다. 이렇게 내장형 필터를 포함한 MCM-D 기판은 MMIC를 flip-chip 방법으로 실장 할 수 있어서 집적화된 밀리미터파 대역 초소형 system 구현에 적용되어 우수한 특성을 나타낼 것으로 기대된다.

• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.7-18
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• 2008

This paper reviews the current development of an ultra-slim SiP for Radio Frequency (RF) application, in which three flip chips, additional passive components and Surface Acoustic Wave (SAW) filters are integrated side-by-side. A systematic investigation is carried out for the design optimization, process and reliability improvement of the package, which comprises several aspects: a design study based on the 3D thermo-mechanical finite element analysis of the packaging, the determination of stress, warpage distribution, critical failure zones, and the figuration of the effects of material properties, process conditions on the reliability of package. The optimized material sets for manufacturing process were determined which can reduce the number of testing samples from 75 to 2. In addition the molded underfilling (MUF) process is proposed which not only saves one manufacturing process, but also improves the thermo-mechanical performance of the package compared with conventional epoxy underfilling process. In the end, JEDEC's moisture sensitivity test, thermal cycle test and pressure cooker tests have also been carried out for reliability evaluation. The test results show that the optimized ultra-slim SiP has a good reliability performance.

• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• 한국정밀공학회지
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• 제28권2호
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• pp.193-201
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• 2011

Clamp type transferring mechanism for package substrate's wet processes was newly developed instead of conventional roller type transferring mechanism. Clamp type transferring mechanism has the advantages of reducing the panel deflection and of minimizing the contact problem between the panel and the transferring mechanism. Individual clamp of the mechanism has two distinct mechanical functions which are perfectly fixing a panel during the transferring and generating adequate tension for the panel. To determine the mechanical parameters of the clamp, panel deflection simulation was conducted and the result was verified by the panel deflection measurement. Also, fixing angle of a clamp could be determined by the free body force analysis of individual clamp. Finally clamp type transferring mechanism was actually manufactured and the transferring performance was verified during the water spraying condition of the package substrate's wet processes.

• 대한전자공학회논문지SD
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• 제43권11호
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• pp.8-13
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• 2006

최근 RF용 탄성표면파 필터는 HTCC 패키지를 이용한 칩스케일 패키지 공법으로 제작되고 있다. 본 연구에서는 HTCC 패키지를 이용하는 대신에 BT 레진 계열의 PCB 기판을 이용하여 $1.4{\times}1.1$과 $2.0{\times}1.4mm$ 규격을 가지는 새로운 SAW RF 필터를 개발하였다. 본 기술을 적용하여 기존대비 약 40% 이상의 재료비 절감효과를 얻을 수 있다. 다층 PCB 기판과 $LiTaO_3$ 탄성표면파 기간간의 플립 본딩 조건을 최적화하였고, 적절한 PCB 재료선정을 통하여 PCB 기판 및 에폭시 라미네이팅 필름간의 열팽창계수 차이로 인해 발생하는 응력을 최소화시켰다. 이렇게 개발된 탄성표면파 필터는 기존의 제품에 비해 신뢰성 및 전기적 특성면에서 향상된 특성을 보였다.

• 한국표면공학회지
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• 제50권3호
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• pp.170-176
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• 2017

EPIG (Electroless Pd/immersion Au) process was studied to replace ENIG (electroless Ni/immersion Au) and ENEPIG (electroless Ni/electroless Pd/immersion Au) processes for bump surface treatment used in high reliable flip chip packages. The palladium and gold layers formed by EPIG process were uniform with thickness of 125 nm and 34.5 nm, respectively. EPAG (Electroless Pd/autocatalytic Au) also produced even layers of palladium and gold with the thickness of 115 nm and 100 nm. TEM results exhibited that the gold layer in EPIG surface had crystalline structure while the palladium layer was amorphous one. After annealing at 250 nm, XPS analysis indicated that the palladium layer with thickness more than 22~33 nm could act as a diffusion barrier of copper interconnects. As a result of comparing the chip shear strength obtained from ENIG and EPIG surfaces, it was confirmed that the bonding strength was similar each other as 12.337 kg and 12.330 kg, respectively.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2010년도 춘계학술발표대회 초록집
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• pp.74-74
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• 2010

모바일 정보통신기기를 중심으로 전자패키지의 초소형화, 고집적화를 위해 플립칩 공법의 적용이 증가되고 있는 추세이다. 플립칩 패키징 접합소재로는 솔더, ICA(Isotropic Conductive Adhesive), ACA(Anisotropic Conductive Adhesive), NCA(Non Conductive Adhesive) 등과 같은 다양한 접합소재가 사용되고 있다. 최근에는 언더필을 사용하는 플립칩 공법보다 미세피치 대응성을 위해 NCP를 이용한 플립칩 공법에 대한 요구가 증가되고 있는데, NCP의 상용화를 위해서는 공정성과 함께 신뢰성 확보가 필요하다. 본 연구에서는 LDI(LCD drive IC) 모듈을 위한 COF(Chip-on-Film) 플립칩 패키징용 NCP 포뮬레이션을 개발하고 이를 적용한 COF 패키지의 신뢰성을 조사하였다. 테스트베드는 면적 $1.2{\times}0.9mm$, 두께 $470{\mu}m$, 접속피치 $25{\mu}m$의 Au범프가 형성된 플리칩 실리콘다이와 접속패드가 Sn으로 finish된 폴리이미드 재질의 flexible 기판을 사용하였다. NCP는 에폭시 레진과 산무수물계 경화제, 이미다졸계 촉매제를 사용하여 다양하게 포뮬레이션을 하였다. DSC(Differential Scanning Calorimeter), TGA(Thermogravimetric Analysis), DEA(Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화거동을 확인하였으며, 본딩 후에는 보이드를 평가하고 Peel 강도를 측정하였다. 최적의 공정으로 제작된 COF 패키지에 대한 HTS (High Temperature Stress), TC (Thermal Cycling), PCT (Pressure Cooker Test)등의 신뢰성 시험을 수행한 결과 양산 적용 가능 수준의 신뢰성을 갖는 것을 확인할 수 있었다.

• 마이크로전자및패키징학회지
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• 제26권4호
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• pp.47-53
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• 2019

Polydimethylsiloxane (PDMS)를 베이스 기판으로 사용하고 이보다 강성도가 높은 polytetrafluoroethylene(PTFE)를 island 기판으로 사용한 soft PDMS/hard PDMS/PTFE 구조의 강성도 경사형 신축 패키지를 형성하고, 이의 신축변형에 따른 저항특성을 분석하였다. PDMS/PTFE 기판패드에 50 ㎛ 직경의 칩 범프들을 anisotropic conductive paste를 사용하여 실장한 플립칩 접속부는 96 mΩ의 평균 접속저항을 나타내었다. Soft PDMS/hard PDMS/PTFE 구조의 신축 패키지를 30% 변형률로 인장시 PTFE의 변형률이 1%로 억제되었으며, PTFE 기판에 형성한 회로저항의 중가는 1%로 무시할 정도였다. 0~30% 범위의 신축변형 싸이클을 2,500회 반복시 회로저항이 1.7% 증가하였다.