• 마이크로전자및패키징학회지
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• 제18권3호
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• pp.67-74
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• 2011

Keys to high wiring density semiconductor packages include flip-chip bonding and build-up substrate technologies. The current issues are the establishment of a fine pitch flip-chip bonding technology and a low coefficient of thermal expansion (CTE) substrate technology. In particular, electromigration and thermomigration in fine pitch flipchip joints have been recognized as a major reliability issue. In this paper, electromigration and thermomigration in Cu/Sn-3Ag-0.5Cu (SAC305)/Cu flip-chip joints and electromigration in Cu/In/Cu flip chip joints are investigated. In the electromigration test, a large electromigration void nucleation at the cathode, large growth of intermetallic compounds (IMCs) at the anode, a unique solder bump deformation towards the cathode, and the significantly prolonged electromigration lifetime with the underfill were observed in both types of joints. In addition, the effects of crystallographic orientation of Sn on electromigration were observed in the Cu/SAC305/Cu joints. In the thermomigration test, Cu dissolution was accelerated on the hot side, and formation of IMCs was enhanced on the cold side at a thermal gradient of about $60^{\circ}C$/cm, which was lower than previously reported. The rate of Cu atom migration was found comparable to that of electromigration under current conditions.

• 한국생산제조학회지
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• 제19권2호
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• pp.157-162
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• 2010

This paper describes the thermal fatigue life prediction models for 95.5Sn-4.0Ag-0.5Cu solder joints of Flip chip package considering Under Bump Metallurgy(UBM). A 3D Finite element slice model was used to simulate the viscoplastic behavior of the solder. For two types of solder bump pitches, simulations were analyzed and the effects of underfill packages were studied. Consequently, it was found out that solder joints with underfill had much better fatigue life than solder joints without underfill, and solder joints with $300{\mu}m$ bump pitch had a longer thermal fatigue life than solder joints with $150{\mu}m$ bump pitch. Through the simulations, flip chip with lead-free solder joints should be designed with underfill and a longer bump pitch.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2005년도 춘계학술발표대회 개요집
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• pp.19-21
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• 2005

The ball shea. tests for ball grid array (BGA) and flip chip packages were carried out with different displacement rates to find out the optimum condition of the displacement rate for this test. The BGA packages consisted of two different kinds of solder balls (eutectic Sn-37wt.%Pb and Sn-3.5wt.%Ag) and electroplated Au/Ni/Cu substrate, whereas the flip chip package consisted of electroplated Sn-37Pb solder and Cu UBM. The packages were reflowed up to 10 times, or aged at 443 K up to 21 days. The variation of the displacement rate resulted in the variations of the shear properties such as shear force, displacement rate at break, fracture mode and strain rate sensitivity. The increase in the displacement rate led to the increase of the shear force and brittleness of solder joints.

• 마이크로전자및패키징학회지
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• 제10권4호
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• pp.81-86
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• 2003

상부 칩과 하부 기판이 모두 Si으로 구성되어 있는 플립칩 패키지 시편을 제조하여 Sn-3.5Ag 솔더범프의 electromigration 거동을 분석하였다. Sn-3.5Ag 솔더범프의 electromigration 테스트 초기부터 파단이 일어나기 직전까지는 플립칩 시편의 저항이 거의 변하지 않았으나, 파단이 발생하는 순간 저항값이 크게 증가하였다. 전류밀도 $3\times 10^4$∼$4\times 10^4$A/$\textrm{cm}^2$에서 Sn-3.5Ag 솔더범프의 electromigration에 대한 활성화 에너지는 ∼0.7 eV로 분석되었다. Sn-3.5Ag 솔더범프의 cathode 부위의 솔더/UBM 계면에서 void의 형성 및 전파에 의해 솔더범프의 파단이 발생하였다.

• 마이크로전자및패키징학회지
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• 제8권2호
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• pp.37-42
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• 2001

The BGA package has been the area array package of choice for several years. Recently, the transition has been to finer pitch configurations called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch. requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and place equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2001년도 Proceedings of 6th International Joint Symposium on Microeletronics and Packaging
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• pp.27-34
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• 2001

The BGA Package has been the area array package of choice for several rears. Recently, the transition has been to finer pitch configuration called Chip Scale Packages (CSP). Several of these package types are available at 0.5 mm pitch, requiring surface mount assemblers to evaluate and optimize various elements of the assembly process. This presentation describes the issues associated with making the transition from BGA to CSP assembly. Areas addressed will include the accuracy of pick and piece equipment, printed wiring board lines and spaces, PWB vias, in-circuit test issues, solder paste printing, moisture related factors, rework and reliability. The transition to 0.5 mm pitch requires careful evaluation of the board design, solder paste selection, stencil design and component placement accuracy. At this pitch, ball and board pad diameters can be as small as 0.25 mm and 0.20 mm respectively. Drilled interstitial vias are no longer possible and higher ball count packages require micro-via board technology. The transition to CSP requires careful evaluation of these issues. Normal paste registration and BGA component tolerances can no longer achieve the required process levels and higher accuracy pick and place machines need to be implemented. This presentation will examine the optimization of these critical assembly operations, contrast the challenges at 0.5 mm and also look at the continuation of the process to incorporate smaller pitch flip chip devices.

• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.49-56
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• 2012

최근 전자 제품의 소형화, 박형화 및 집적화에 따라 칩과 기판을 연결하는 범프의 미세화가 요구되고 있다. 그러나 범프의 미세화는 직경 감소와 UBM의 단면적 감소로 인하여 전류 밀도를 증가시켜 전기적 단락을 야기할 수 있다. 특히 범프에서 형성되는 금속간화합물과 KV의 형성은 전기적 및 기계적 특성에 큰 영향을 줄 수 있다. 따라서 본 논문에서는 유한요소해석을 이용하여 플립칩 범프의 열변형을 분석하였다. 우선 TCT의 온도조건을 통하여 플립칩 패키지의 열변형 특성을 분석한 결과, 범프의 열 변형이 시스템의 구동에 큰 영향을 미칠 수 있음을 확인하였다. 그리고 범프의 열변형 특성에 큰 영향을 미칠 것을 생각되는 IMC층의 두께와 범프의 직경을 변수로 선정하여 온도변화, 열응력 및 열변형에 대한 해석을 수행하였으며, 이를 통하여 IMC층이 범프에 영향을 미치는 원인에 대한 분석을 수행하였다.

• 마이크로전자및패키징학회지
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• 제28권2호
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• pp.45-50
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• 2021

Flip chip 제품의 난이도 증가에 따라 solder wetting 및 신뢰성 관점에서 강점을 갖는 flux 소재에 대한 관심이 높아지고 있다. 지용성 flux의 경우 별도의 세정 공정이 없기 때문에 공정 효율화 측면에서 유리하나, 리플로우 공정이후 반응을 마친 잔여물이 잔존하게 되는 경우 Cu migration 및 delamination을 발생시킬 수 있다. 본 연구에서는 저잔사 flux 구현을 위해 신규 resin에 적합한 solvent 및 activator를 변경 하였으며, package 환경에서 non-wet 및 신뢰성 개선 유무를 확인하였다. 저장 안정성 평가를 통해 신규 소재에 대한 안정성을 확보하였으며, boiling point가 상이한 solvent와 activator 2종 적용 및 activator 함량 증대를 통해 non-wet 미 발생 flux 소재를 확보하였다. 해당 소재에 대한 신뢰성 검증 이후 평면 분석 결과 flux residue 기인성 delamination 현상은 발견되지 않았으며, 이를 통해 저잔사 flux에 대한 최종 조성을 확보하였다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2008년도 춘계학술대회 논문집
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• pp.15-16
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• 2008

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2011년도 춘계학술대회 논문집
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• pp.821-822
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• 2011