• 공업화학
• /
• 제30권4호
• /
• pp.487-492
• /
• 2019

주름 개선을 위한 활성물질인 아데노신의 경피 투과를 위해 나노 플렉시블 베시클에 포집을 시도하였다. 나노 플렉시블 베시클은 인지질, 에탄올, lysolecithin으로 구성되는데, 수화 과정에서 형성된 액정 상을 물속에 분산시켜 만드는 액정형 베시클이다. 본 연구에서는 베시클 입자크기에 영향을 미치는 요인을 알아보기 위하여 실험계획법 중 하나인 다구찌 방법을 적용하였다. 다구찌 직교 배열을 활용하여 베시클 입자크기에 대한 망소 특성의 S/N 비를 산출하였다. 베시클 구성성분에서 에탄올과 lysolecithin 비율, 수화 과정에서 투입되는 수용액 양 등이 베시클 입자크기에 큰 영향을 미치는 주요 인자들이고, ANOVA 분석을 통해 이들 인자가 신뢰수준 95%에서 유의함을 확인하였다.

• 천문학논총
• /
• 제21권2호
• /
• pp.67-74
• /
• 2006

We have developed a control electronics system for an infrared detector array of KASINICS (KASI Near Infrared Camera System), which is a new ground-based instrument of the Korea Astronomy and Space science Institute (KASI). Equipped with a $512{\times}512$ InSb array (ALADDIN III Quadrant, manufactured by Raytheon) sensitive from 1 to $5{\mu}m$, KASINICS will be used at J, H, Ks, and L-bands. The controller consists of DSP(Digital Signal Processor), Bias, Clock, and Video boards which are installed on a single VME-bus backplane. TMS320C6713DSP, FPGA(Field Programmable Gate Array), and 384-MB SDRAM(Synchronous Dynamic Random Access Memory) are included in the DSP board. DSP board manages entire electronics system, generates digital clock patterns and communicates with a PC using USB 2.0 interface. The clock patterns are downloaded from a PC and stored on the FPGA. UART is used for the communication with peripherals. Video board has 4 channel ADC which converts video signal into 16-bit digital numbers. Two video boards are installed on the controller for ALADDIN array. The Bias board provides 16 dc bias voltages and the Clock board has 15 clock channels. We have also coded a DSP firmware and a test version of control software in C-language. The controller is flexible enough to operate a wide range of IR array and CCD. Operational tests of the controller have been successfully finished using a test ROIC (Read-Out Integrated Circuit).

• 한국정보기술응용학회:학술대회논문집
• /
• 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
• /
• pp.285-288
• /
• 2005

We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.

• 소성∙가공
• /
• 제15권1호
• /
• pp.9-14
• /
• 2006

In the present research, the simultaneous punching of ultra small size hole of $2\~10\;{\mu}m$ in diameter on flat rolled thin metal foils was conducted with elastic polymer punch. Workpiece used in the present investigation were the rolled pure copper of $3{\mu}m$ in thickness and CP titanium of 1.5fm in thickness. The metal foils were punched with the dies and arrays of circular and rectangular holes were made. The process set-up is similar to that of the flexible rubber pad farming or Guerin process. Arrays of holes were punched successfully in one step forming. The punched holes were examined in terms of their dimensions. The effects of the wafer die hole dimension and heat treatment of the workpiece on ultra small size hole formation of the thin foil were discussed. The process condition such as proper die shape, pressure, pressure rate and diameter-thickness ratio (d/t) were also discussed. The results in this paper show that the present method can be successfully applied to the fabrication of ultra small size hole away in a one step operation.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2002년도 춘계학술대회 논문집 디스플레이 광소자 분야
• /
• pp.45-48
• /
• 2002

Poly(3-hexylthiophene) or P3HT based organic thin film transistor (OTFT) array was fabricated on flexible poly carbonate substrates and the electrical characteristics were investigated. As the gate dielectric, a dual layer structure of polyimide-$SiO_2$ was used to improve the roughness of $SiO_2$ surface and further enhancing the device performance and also source-drain electrodes were $O_2$ plasma treated for improvement of the electrical properties, such as drain current and field effect mobility. For the active layer, polymer semiconductor, P3HT layer was printed by contact-printing and spin-coating method. The electrical properties of OTFT devices printed by both methods were evaluated for the comparison. Based on the experiments, P3HT-based OTFT array with field effect mobility of 0.02~0.025 $cm^{2}/V{\cdot}s$ and current modulation (or $I_{on}/I_{off}$ ratio) of $10^{3}\sim10^{4}$ was fabricated.

• Journal of Power Electronics
• /
• 제16권2호
• /
• pp.553-563
• /
• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• 조명전기설비학회논문지
• /
• 제19권2호
• /
• pp.131-137
• /
• 2005

보호계전기는 고장에 의해 파생되는 단락$\cdot$지락 사고로부터 전력 시스템을 보호하기 위하여 널리 사용되고 있다. 전통적으로 디지털보호계전기는 디지털신호처리 프로세서 혹은 마이크로프로세서로 구현되는데 본 연구는 이를 고성능$\cdot$고효율$\cdot$다기능의 단일칩으로 구현하기 위한 하드웨어 설계 기술에 관해 다룬다. 제작된 디지털보호계전기는 FPGA(Field Programmable Gate Array)로 구현하였고 16KSPS이상의 처리 성능을 가지며 평균 오차율 $0.03(\%)$미만으로 보호계전알고리즘을 수행할 수 있다.

• ETRI Journal
• /
• 제31권6호
• /
• pp.717-724
• /
• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• ETRI Journal
• /
• 제30권5호
• /
• pp.747-749
• /
• 2008

We introduce a pixel-structured scintillator realized on a flexible polymeric substrate and demonstrate its feasibility as an X-ray converter when it is coupled to photosensitive elements. The sample was prepared by filling $Gd_2O_2S:Tb$ scintillation material into a square-pore-shape cavity array fabricated with polyethylene. For comparison, a sample with the conventional continuous geometry was also prepared. Although the pixelated geometry showed X-ray sensitivity of about 58% compared with the conventional geometry, the resolving power was improved by about 70% above a spatial frequency of 3 $mm^{-1}$. The spatial frequency at 10% of the modulation-transfer function was about 6 $mm^{-1}$.

• Journal of Computing Science and Engineering
• /
• 제9권2호
• /
• pp.39-50
• /
• 2015

Genetic algorithm (GA) and particle swarm optimization (PSO) are two excellent approaches to multimodal optimization problems. However, slow convergence or premature convergence readily occurs because of inappropriate and inflexible evolution. In this paper, a novel optimization algorithm with a flexible grid optimization (FGO) is suggested to provide adaptive trade-off between exploration and exploitation according to the specific objective function. Meanwhile, a uniform agents array with adaptive scale is distributed on the gird to speed up the calculation. In addition, a dominance centroid and a fitness center are proposed to efficiently determine the potential guides when the population size varies dynamically. Two types of subregion division strategies are designed to enhance evolutionary diversity and convergence, respectively. By examining the performance on four benchmark functions, FGO is found to be competitive with or even superior to several other popular algorithms in terms of both effectiveness and efficiency, tending to reach the global optimum earlier. Moreover, FGO is evaluated by applying it to a parameter decision in a least squares support vector machine (LS-SVM) to verify its practical competence.