• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.286-291
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• 2015

For highly scalable NAND flash memory applications, a compact ($4F^2/cell$) nonvolatile memory architecture is proposed and investigated via three-dimensional device simulations. The back-channel program/erase is conducted independently from the front-channel read operation as information is stored in the form of charge at the backside of the channel, and hence, read disturbance is avoided. The memory cell structure is essentially equivalent to that of the fully-depleted transistor, which allows a high cell read current and a steep subthreshold slope, to enable lower voltage operation in comparison with conventional NAND flash devices. To minimize memory cell disturbance during programming, a charge depletion method using appropriate biasing of a buried back-gate line that runs parallel to the bit line is introduced. This design is a new candidate for scaling NAND flash memory to sub-20 nm lateral dimensions.

• Journal of ILASS-Korea
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• v.3 no.2
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• pp.24-33
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• 1998

The characteristics of liquefied butane spray are expected to be different from conventional diesel fuel spray, because a kind of flash boiling spray is expected when the back pressure is below the saturation vapor pressure of the butane(0.23MPa at $25^{\circ}C$). An accumulator type pintle injector and its fuel delivery system has been simulated in ruder to give injection pressure, needle lift and rate of fuel injected. The governing equation were solved by finite difference metho. The injection duration was controlled by solenoid valve. Spray behaviors such as a transient spray tip penetration, spray angle and SMD were calculated based on the empirical correlations in case that the back pressure is both above the vapor pressure of the butane and below that of butane. When the back preassure is below the vapor pressure of the fuel, conventional correlation is modified to represent the effect of flash boiling.

• Journal of Advanced Navigation Technology
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• v.15 no.5
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• pp.801-807
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• 2011

If the System is downed by computer or disasters, it can have a bad influence on the reliability of the corporation and business continuity because all companies are computerized. Accordingly, interest on the business continuity without the loss of data in the corporate is increasing. In this paper, system faults have been defined as physical faults and logical faults and CDP solution using Flash SSD has been proposed for enhancing IOPS which is needed for realtime-backup. In order to measure IOPS performance of the CDP using Flash SSD, we constructed an experimental system. From the results we can see that IOPS performance of CDP using Flash SSD is about 50 times more effective than that of the S-ATA.

• 한국전산유체공학회:학술대회논문집
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• 2008.08a
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• pp.48.2-48.2
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• 2008

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.452-454
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• 2001

This paper described the calculation results of lightning flashover rate on the 345kV and 154kV transmission system of KEPCO. The back-flashover rate and shielding failure rate was calculated by FLASH(lightning flashover rate calculation program from IEEE) and KEPRI's own program which is based on the EGM(Electro Geometrical Model) method. The estimated lightning flashover late of 345kV transmission system of double circuit was 1.0 flash per 100km-year, and the lightning flashover rate of 154kV transmission line was 2.0 flash Per 100km-year approximately.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.9
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• pp.898-903
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• 2010

Popularity of smartphones such as Google Android phones and Apple iphones, is increasing the demand on more reliable high performance file system for flash memory. In this paper, we propose two techniques to improve the performance of YAFFS (Yet Another Flash File System), while enhancing the reliability of the system. Specifically, we first propose to manage metadata and user data separately on segregated blocks and indexing information piggy-back technique for reducing mount time and also enhancing performance. Second, we tailor the wear-leveling to the segregated metadata and user data blocks. Performance evaluation results based on real hardware system with 1GB NAND flash memory show that the YAFFS with our proposed techniques realized outperforms the original YAFFS by six times in terms of mount speed and five times in terms of benchmark performance, while reducing the average erase count of blocks by 14%.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.773-774
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• 2012

• 전기의세계
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• v.29 no.1
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• pp.65-72
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• 1980

Arstrong-Whitehead theory on effective shielding and shielding failure is extended so that it is applicable to vertical line configuration the existing approaches on back-flash rate calculation are summerized and compared in particular on Model Line, and the usefulness of the whitehead approach is suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.