• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.537-542
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• 2014

The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage ($V_T$) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Korean Society of Safety
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• v.24 no.2
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• pp.42-47
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• 2009

The flash point and the AIT(auto-ignition temperature) are the most important combustible properties used to determine the potential for the fire and explosion hazards of flammable material. In order to know the accuracy of data in MSDS(Material Safety Data Sheet), the flash point of n-acids were measured by using Pensky-Martens closed cup tester(ASTM D93), Setaflash closed cup tester(ASTM D3278), Tag open cup tester(ASTM D1310) and Cleveland open cup tester(ASTM D92). Also, the AIT of n-acids were measured by using ASTM E659-78 tester. The measured the flash points and the AIT were compared with literatures and MSDS in KOSHA. The measured the flash points and the AIT were different from those in literatures and MSDS. Therefore, This paper shows that it is needed to investigate the MSDS compatibility of n-acids for the fire safety objectives.

• Journal of the Korean Institute of Gas
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• v.13 no.4
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• pp.40-45
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• 2009

In order to investigate the compatibility of data in MSDS(Material Safety Data Sheet), the flash point of xylene isomer was measured by using Pensky-Martens closed cup (ASTM D93), Setaflash closed cup(ASTM D3278), Tag open cup(ASTM D1310), and Cleveland open cup (ASTM D92) testers. Also, the AITs(autoignition temperatures) of xylene isomers were measured by using ASTM E659-78 tester. The measured the flash points and the AITs were compared with literatures and MSDS in KOSHA(Korea Occupational Safety and Health Agency). The measured the flash points and the AITs were different from those in literatures and MSDS. As a result, this paper is shown that it is needed to investigate combustion characteristics of xylene isomer for the fire safety objectives.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.5
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• pp.585-590
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• 2014

A permanent vertical magnetization should be obtained to counteract induced vertical magnetization due to the earth's background field during the Flash D demagnetization process. A vertical susceptibility is needed to calculate a extra-permanent magnetization, which is needed to control the permanent vertical magnetization in stage 2 of Flash D demagnetization and added to the final vertical permanent magnetization. Two susceptibilities were found in this paper. One is obtained from the extra-magnetization. The other is obtained by magnetic field measurement from the scaled physical vessel when the vessel is excited by vertical magnetic field. The initial susceptibility by the extra-magnetization was 0.101~0.109 and the one from the measured magnetic field was 0.122. Two susceptibilities have a good agreement each other. From this paper, it is found that the susceptibility is able to appllied to calculate the extr-magnetization.

• Journal of the Korean Society of Hazard Mitigation
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• v.10 no.4
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• pp.81-88
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• 2010

As there occurs recently and frequently a flash flood due to the climate change, a sudden local flood of great volume and short duration caused by heavy or excessive rainfall in a short period of time over a small area, it is increasing that significant danger and loss of life and property in Korea as well as the whole world. Since a flash flood usually occurs as the result of intense rainfall over small steep slope regions and has rapid runoff and debris flow, a flood rises quite quickly with little or no advance warning to prevent flood damage. The aim of this study is to quantify the severity of flash food by estimation of a flash flood index(FFI) from probability rainfall data in a study basin. FFI-D-F(FFI-Duration-Frequency) curves that present the relative severity of flash flood are developed for a study basin to provide regional basic information for the local flood forecasting and warning system particularly in ungauged catchments. It is also expected that FFI-D-F curves can be utilized for evaluation on flash flood mitigation ability and residual flood risk of both existing and planned flood control facilities.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.566-571
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• 2014

Channel-stacked 3D NAND flash memory is very promising candidate for the next-generation NAND flash memory. However, there is an inherent issue on cell size variation between stacked channels due to the declined etch slope. In this paper, the effect of the cell variation on the incremental step pulse programming (ISPP) characteristics is studied with 3D TCAD simulation. The ISPP slope degradation of elliptical channel is investigated. To solve that problem, a new programming method is proposed, and we can alleviate the $V_T$ variation among cells and reduce the total programming time.